Template-Shaped Semiconductor Fins for Self-Aligned Gate Endcaps
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Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices poses challenges due to constraints on semiconductor processes, particularly in achieving reduced external resistance and capacitance, and addressing short channel effects and leakage issues, which are exacerbated by mask registration errors affecting gate and trench contact endcap dimensions.
Innovation Solution
The approach involves fin shaping using templates with alternating insulating layers of different etch rates, enabling the growth of semiconductor fins within a template to form desired geometries, and employing self-aligned gate and trench contact endcap structures without requiring extra length for mask registration, thus reducing device variability and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multi-gate transistor fabrication processes are used, then device density increases through scaling, but mask registration errors cause variability in gate and trench contact endcap dimensions
Solution Approach 1:
The gate endcap structure is self-aligned to the trench contact, eliminating the need for separate lithographic patterning steps. The endcap forms automatically through conformal deposition processes that follow the trench contact geometry, making the structure self-defining and immune to mask registration errors.
Solution Approach 2:
The trench contact is formed first as a preliminary structure that serves as the template for the subsequent gate endcap formation. By establishing the trench contact geometry beforehand, the endcap position and dimensions are predetermined, eliminating the need for additional lithographic alignment steps.
2Manufacturing precision
If additional endcap length is added to compensate for mask mis-registration, then dimensional variability is reduced, but device layout area increases
Solution Approach 1:
The self-aligned formation mechanism eliminates the need for excessive endcap length compensation. Since the endcap dimensions are determined by the trench contact geometry rather than separate lithographic patterns, no additional area is required to accommodate mask registration tolerances.
3Ease of manufacture
If conventional lithographic patterning is used for gate and trench contact formation, then process compatibility is maintained, but external resistance and capacitance increase
Solution Approach 1:
The mechanical lithographic patterning process is replaced with a conformal deposition-based self-aligned formation process. Instead of using lithographic masks to define the endcap geometry, the structure is formed by sequential conformal deposits that automatically align to the trench contact, eliminating lithographic alignment errors and their impact on electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances device performance by reducing external resistance and capacitance, improving short channel effects, and minimizing leakage, while eliminating the need for additional endcap length to account for mask mis-registration, thereby improving transistor layout density and energy efficiency.
Implementation Method 1
fin shaping using templates with alternating insulating layers of different etch rates, enabling the growth of semiconductor fins within a template to form desired geometries
Data Source
AI summary
Fin shaping using templates, and integrated circuit structures resulting therefrom, are described. For example, integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has a vertical portion and one or more lateral recess pairs in the vertical portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack. A second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.