FinFET Liner Structure for Void-Free Shallow Trench Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing FinFET fabrication methods face challenges with high aspect ratios in fin structures, leading to reduced gap filling capability and potential voids in shallow trench isolation (STI) structures due to increased aspect ratios.
Innovation Solution
A semiconductor device structure and method involving a liner structure with a first insulating liner layer of silicon oxide and a second insulating liner layer of silicon nitride or oxynitride, which prevents oxidation and charge trapping, and improves gap filling by forming isolation features between fin structures, ensuring effective shallow trench isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fin structures are made very high to increase device density and performance, then the current flow and device density are improved, but the aspect ratio of the gaps between fin structures increases, reducing gap filling capability and causing voids in STI structures
Solution Approach 1:
The gap filling process is divided into multiple sequential steps: first forming a mandrel structure, then depositing a first dielectric material, removing the mandrel, and depositing a second dielectric material. This segmentation allows each step to be optimized independently, enabling complete gap filling in high aspect ratio trenches without voids.
Solution Approach 2:
A mandrel structure is formed in advance within the gaps between fin structures before the actual dielectric filling. This preliminary structure serves as a template that guides the sequential deposition process, ensuring that materials are deposited uniformly and completely fill the high aspect ratio gaps.
2Device complexity
If conventional single-layer insulating structures are used in STI, then the process is simple, but oxidation of fin structures and charge trapping occur, reducing device reliability
Solution Approach 1:
The STI structure uses a composite of two different dielectric materials: a first dielectric material (such as silicon oxide) and a second dielectric material (such as silicon nitride or oxynitride). Each material provides different properties - the first material provides good gap filling and adhesion, while the second material provides oxidation protection and charge trapping prevention, achieving enhanced reliability without excessive complexity.
Solution Approach 2:
Different regions of the STI structure are assigned different dielectric materials based on their specific functional requirements. The first dielectric material is placed in direct contact with the fin structures where adhesion and gap filling are critical, while the second dielectric material is placed where oxidation protection and electrical isolation are needed, optimizing performance at each location.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the gap filling capability, prevents void formation in STI structures, and protects fin structures from oxidation, thereby improving the reliability and performance of FinFETs.
Implementation Method 1
a liner structure including a first insulating liner layer of silicon oxide and a second insulating liner layer of silicon nitride or oxynitride over the first insulating liner layer
Implementation Method 2
The gap filling capability is reduced due to an increase in the aspect ratio of those gaps/trenches, and hence voids may be formed in the shallow trench isolation (STI) structures
Data Source
AI summary
A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a first fin structure protruding from the first region of the semiconductor substrate and having a first portion and a second portion over the first portion. The semiconductor device structure also includes a liner structure including a first insulating liner layer and second insulating liner layer. The first insulating liner layer has a bottom portion covering the semiconductor substrate and a sidewall portion covering a sidewall of the first portion of the first fin structure. The second insulating liner layer is over the bottom portion and the sidewall portion of the first insulating liner layer and extends on a top surface of the sidewall portion of the first insulating liner layer. The semiconductor device structure also includes an isolation feature over the liner structure.