Through Via Structure Placement for Resistance Tuning in Semiconductor Wiring
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Solution Overview
Problem
Semiconductor devices with through via structures face challenges in adjusting resistance and mitigating the reduction of electrical performance of integrated circuit layers, particularly when these structures are used as electrodes and are integrated near transistors.
Innovation Solution
The semiconductor device incorporates multiple through via structures with varying diameters and heights, strategically positioned apart from the integrated circuit layer, allowing for adjustable resistance and reduced electrical performance impact by using these structures to connect metal wiring layers across the substrate, thereby optimizing signal and power transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through via structures are used as electrodes to increase capacity and bandwidth, then data processing capability is improved, but resistance adjustment becomes difficult and electrical performance of integrated circuit layer is reduced
Solution Approach 1:
The patent applies local quality by positioning through via structures in specific keep-out zones away from the integrated circuit layer, and by varying the diameters and heights of different through via structures to achieve localized resistance adjustment. This allows the through vias to serve their function while minimizing their impact on the electrical performance of the integrated circuit layer.
2Device complexity
If through via structures are positioned near integrated circuit layer to optimize wiring, then device complexity is reduced, but electrical performance of integrated circuit layer deteriorates
Solution Approach 1:
The patent introduces keep-out zones as intermediary regions that separate the through via structures from the integrated circuit layer. These zones act as buffer regions that allow wiring optimization through via structures while preventing direct interference with the electrical performance of the integrated circuit layer.
3Ease of manufacture
If through via structures are made with uniform dimensions for ease of manufacturing, then manufacturing precision is improved, but resistance adjustment capability is lost
Solution Approach 1:
The patent applies parameter changes by varying the diameters and heights of different through via structures to achieve specific resistance values. Different via sizes are used in different locations to optimize resistance characteristics while maintaining compatibility with standard fabrication processes.
Data Source
AI summary
A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.