Variable-Fin Multi-Gate Transistor for Mixed-Voltage SoCs
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Solution Overview
Problem
Semiconductor devices with FinFET architecture face challenges in supporting both low voltage and high voltage devices within a single System on a Chip (SoC) due to performance degradation under high voltage stress conditions, as aggressively scaled fin dimensions improve subthreshold characteristics for low voltage devices but degrade high voltage performance.
Innovation Solution
The implementation of differential fin transistors with varying fin width and height, which includes a narrower fin width at the source side and a wider fin width at the drain side to reduce gate-induced drain leakage and improve reliability, while maintaining compatibility with conventional tri-gate formation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform fin dimensions are used, then manufacturing is simplified, but performance cannot accommodate both low voltage and high voltage devices
Solution Approach 1:
Instead of uniform fin dimensions, the patent implements local quality variations by creating regions with different fin widths. The first region has dimensions optimized for low voltage devices while the second region has dimensions optimized for high voltage devices, allowing a single fin structure to support multiple voltage operatings.
Solution Approach 2:
The fin structure achieves universality by being designed to support both low voltage and high voltage device operations within the same transistor. The multi-region fin structure with varying widths enables the single fin to serve multiple functional requirements that would traditionally require separate devices.
Data Source
Figure 1A
Figure 1B~1C
Figure 2A
AI summary
An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.