Comb-Shaped Bit Line Layout for Higher-Density DRAM Cells
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Solution Overview
Problem
As semiconductor devices, such as DRAM, shrink in dimension, it becomes increasingly difficult to fabricate interconnecting structures for memory cells, and existing designs struggle to achieve higher device density and performance while maintaining efficient fabrication processes.
Innovation Solution
The implementation of a comb-shaped or fence-shaped bit line structure with pins optionally connected to transistors, fabricated using a dual damascene process, which allows for improved functionality and performance by simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional interconnecting structures are used in shrinking DRAM devices, then fabrication complexity increases, but device density and performance improvement is limited
Solution Approach 1:
The bit line is segmented into multiple pins extending toward the substrate, with each pin serving as an independent connection point. This segmentation allows for simplified fabrication processes while achieving higher device density, as each pin can be independently formed and connected to transistor structures without requiring complex interconnecting structures
Solution Approach 2:
The bit line structure transitions from a conventional planar configuration to a three-dimensional comb-shaped or fence-shaped structure with pins extending vertically toward the substrate. This dimensional change enables more efficient use of vertical space and simplifies the fabrication process by allowing pins to be formed through direct extension rather than complex lateral interconnections
2Adaptability or versatility
If various cell designs are implemented to achieve higher device density, then design versatility improves, but fabrication difficulty increases
Solution Approach 1:
The comb-shaped or fence-shaped bit line structure serves multiple functions: it provides electrical connections to transistors, acts as isolation structures between adjacent cells, and enables various cell design configurations. This universal structure simplifies fabrication across different cell designs while maintaining design versatility for achieving higher device density
Data Source
AI summary
The present disclosure relates to a semiconductor device and a fabricating method thereof, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.