Stacked Imaging Readout Circuit Layout for Low-Noise Pixels
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Solution Overview
Problem
In solid-state imaging devices, increasing the gate area of amplification transistors to reduce noise leads to sensitivity differences between photoelectric conversion units due to transistor size disparities, making it difficult to minimize noise while maintaining a small layout area.
Innovation Solution
The implementation of a solid-state imaging device with first and second transistor cells arranged adjacent to each other, where the amplification transistors share a main electrode region, allowing for expanded gate areas without increasing the layout area, and the sensor pixels and readout circuits are stacked on separate substrate sections to reduce optical sensitivity differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate area of the amplification transistor is increased to reduce noise, then noise is reduced, but sensitivity difference occurs between photoelectric conversion units due to transistor size variation
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked arrangement of transistor cells. By stacking multiple transistor cells vertically on different substrate sections, the gate area can be increased without expanding the lateral layout area, thus reducing noise while maintaining sensitivity uniformity across photoelectric conversion units.
Solution Approach 2:
The patent merges multiple transistor cells into a stacked configuration where adjacent transistor cells share common diffusion layers. This merging approach increases the effective gate area for noise reduction while the shared diffusion layers ensure consistent electrical characteristics and sensitivity across all photoelectric conversion units.
2Object-affected harmful factors
If the gate area of the amplification transistor is increased to reduce noise, then noise is reduced, but the layout area of transistors increases
Solution Approach 1:
The patent utilizes vertical stacking of transistor cells on different substrate sections to increase gate area. This three-dimensional arrangement allows the gate area to be expanded in the vertical dimension rather than the lateral dimension, thereby reducing noise without increasing the planar layout area occupied by the transistor circuit.
Solution Approach 2:
The stacked transistor cells are designed to perform multiple functions: each cell contributes to noise reduction through increased gate area while simultaneously maintaining compact layout through vertical integration. The shared diffusion layers provide common electrical nodes that serve multiple transistors, achieving space efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise while maintaining a compact layout area by ensuring uniform sensitivity across photoelectric conversion units and allowing for the expansion of gate areas of amplification transistors.
Implementation Method 1
a sensor pixel that performs photoelectric conversion
Data Source
AI summary
The disclosed device reduces noise while suppressing an increase in layout area of transistors included in a readout circuit. This solid-state imaging device includes: a first substrate section; a second substrate section disposed on one side of the first substrate section; a readout circuit; and first and second transistor cells each having, for each readout circuit, a plurality of transistors included in the readout circuit, the first and second transistor cells being arranged adjacent to each other. In addition, the plurality of transistors includes amplification transistors, a sensor pixel is provided on the first substrate section, the readout circuit and the first and second transistor cells are provided on the second substrate section, the amplification transistors of the first and second transistor cells are arranged adjacent to each other, and a first main electrode region of a pair of main electrode regions of each of the amplification transistors is shared.