Plasma Damage Protection in Semiconductor Logic Circuits
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Solution Overview
Problem
In semiconductor device manufacturing, the low contact density in logic circuit regions leads to plasma damage during bit metal formation, which increases chip area and delay performance, as existing methods for plasma damage protection are inefficient and affect chip size and performance.
Innovation Solution
The introduction of dummy bit contacts in the well contact region of logic circuit regions during the manufacturing process, which discharge plasma charge without increasing chip area or degrading delay performance, using a layout that alternates dummy DBLCTs with regular DBLCTs to minimize parasitic capacitance and prevent plasma damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy elements for plasma damage protection are added to logic circuit region, then plasma damage is prevented, but chip area increases and delay performance degrades
Solution Approach 1:
The patent combines dummy bit contacts with well contact regions, merging the plasma damage protection function into existing structural elements. The dummy DBLCTs are formed in the well contact region where well contacts are already present, so no additional chip area is required beyond what is already allocated for well contacts.
Solution Approach 2:
The well contact region serves multiple functions: it provides well contacts for transistor operation and simultaneously hosts dummy bit contacts for plasma damage protection. This multi-functionality allows plasma damage prevention without dedicating separate space solely for protection elements.
2Reliability
If dummy elements for plasma damage protection are added to logic circuit region, then plasma damage is prevented, but delay performance degrades
Solution Approach 1:
By merging dummy bit contacts with well contact regions, the patent eliminates the need for separate protection elements that would add to signal paths. The dummy contacts are integrated into existing well contact locations, so they do not create additional delay paths for logic operations.
3Area of stationary object
If contact density in logic circuit region is low, then chip area is reduced, but plasma damage occurs during bit metal formation
Solution Approach 1:
The patent applies local quality by creating high contact density specifically in well contact regions where dummy bit contacts are formed, while maintaining low contact density elsewhere in the logic circuit region. This localized approach provides plasma damage protection exactly where needed without globally increasing chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces plasma damage in logic circuit regions by efficiently disposing dummy bit contacts, maintaining chip area and performance while preventing plasma-induced transistor failures and yield reduction.
Implementation Method 1
a gate coupled to a DBLCT is subjected to plasma damage by plasma charge generated in the formation of the DBLCT
Data Source
AI summary
An increase in chip area and a deterioration of delay performance are reduced without dummy cells or dummy gates for plasma damage, suppressing an increase in the capacitance of dummy cells or dummy gates and a deterioration of wiring. In the case where bit wires or bit contacts used for the DRAM cell region of a circuit block are used as wires and contacts for a logic circuit region, gate electrodes affected by plasma damage are automatically analyzed after the completion of placement and routing. The well contact region (well potential diffusion layer) of the logic circuit region contains dummy contacts for plasma damage.