Metal Gate Contact Etch Stop Layout for Self-Aligned Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and costs.
Innovation Solution
A method for fabricating semiconductor devices involves forming gate dielectric layers, dummy gate structures, and metal gate structures, along with etching and deposition processes to create protection caps and etching stop layers, which enables precise control and self-aligned formation of source/drain contacts and via contacts, improving device reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty and reliability increase
Solution Approach 1:
The method performs preliminary patterning of the interlayer dielectric layer and source/drain contact formation before final via hole etching. This preliminary action establishes precise alignment references that guide subsequent processing steps, enabling accurate contact formation even at reduced feature sizes where traditional alignment methods fail.
Solution Approach 2:
The patent introduces an intermediary etch stop layer between the interlayer dielectric and the underlying structures. This intermediary layer serves as a controlled interface that facilitates precise etching termination and provides a reference plane for alignment, thereby simplifying the overall fabrication process complexity while maintaining high precision.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but manufacturing precision requirements increase
Solution Approach 1:
The method employs self-aligned processes where the preliminary patterned structures automatically serve as alignment references for subsequent steps. The source/drain contact regions and via holes are formed using the same patterned features as guides, eliminating the need for separate alignment operations and achieving high precision without additional complexity.
Solution Approach 2:
The interlayer dielectric is preliminarily patterned to define the exact locations of source/drain contacts and via holes before final formation. This preliminary patterning creates permanent alignment references that ensure sub-10nm precision in contact placement, meeting the stringent manufacturing precision requirements of advanced node devices.
3Reliability
If conventional etching processes are used at smaller feature sizes, then material loss increases and RC delay worsens
Solution Approach 1:
The etching process uses the etch stop layer as a feedback reference for termination. When the etch front reaches the etch stop layer, the process automatically terminates, preventing over-etching and material loss. This feedback mechanism ensures precise etching depth control and protects underlying structures from damage, maintaining device reliability at small feature sizes.
Solution Approach 2:
The etch stop layer is deposited beforehand as a protective cushion between the etching process and sensitive underlying structures. This cushion layer absorbs the mechanical and chemical stress of the etching process, preventing direct contact between the etchant and the interlayer dielectric or substrate, thereby reducing material loss and preventing damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and performance of semiconductor devices by allowing precise control over etching processes, reducing material loss, and improving RC delay, thus addressing the challenges of smaller feature sizes and increasing complexity in semiconductor fabrication.
Implementation Method 1
a selective deposition process is performed to form a first etch stop layer on the substrate, the selective deposition process having a faster deposition rate on the protection cap than on the source/drain contact
Data Source
AI summary
A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.