FinFET With Dislocation Planes Reducing Leakage Current
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Solution Overview
Problem
As semiconductor devices shrink, the short channel leakage effect becomes significant, leading to inadequate gate control over the channel region, resulting in increased leakage current, which conventional planar transistors struggle to mitigate effectively.
Innovation Solution
The implementation of fin field effect transistors (FinFETs) with a gate structure that wraps around the active region like an upside-down U, combined with the formation of dislocation planes through pre-amorphous implantation, tensile film layers, and anneal processes to enhance electron mobility and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistors are used, then manufacturing is simpler, but gate control over channel region deteriorates leading to increased leakage current
Solution Approach 1:
The patent transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins protruding from substrate. The gate wraps around the fin structure, providing control from top and sidewalls, effectively adding dimensional control to overcome short channel effects and reduce leakage current in deep sub-30nm devices
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but leakage current increases due to short channel effect
Solution Approach 1:
By creating vertical fin structures that protrude from the substrate surface, the patent extends the channel length in the vertical dimension while maintaining small lateral footprint. This allows continued scaling for high integration density while the extended vertical channel provides better gate control to suppress leakage current
Solution Approach 2:
The gate structure wraps around the fin structure like an upside-down U, with gate material enclosing the channel region from multiple sides. This nested configuration enhances gate control over the channel, effectively suppressing short channel leakage effects even as device dimensions are reduced
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FinFET design with dislocation planes improves electron mobility and effectively reduces leakage current by enhancing the gate's control over the channel region, particularly in deep sub-30 nanometer dimensions, where conventional transistors fail.
Implementation Method 1
applying a first pre-amorphous implantation (PAI) process to the substrate and forming a first PAI region underlying the trench as a result of the first PAI process
Implementation Method 2
converting the first PAI region into a first dislocation plane underlying the trench using a first anneal process
Implementation Method 3
The implementation of fin field effect transistors (FinFETs) with a gate structure that wraps around the active region like an upside-down U, combined with the formation of dislocation planes through pre-amorphous implantation, tensile film layers, and anneal processes to enhance electron mobility
Data Source
AI summary
A device comprises a first semiconductor fin over a substrate, a second semiconductor fin over the substrate, wherein the first semiconductor fin and the second semiconductor fin are separated by a first isolation region, a first drain/source region coupled to the first semiconductor fin and the second semiconductor fin and a first dislocation plane underlying the first isolation region, wherein the first dislocation plane extends in a first direction in parallel with a longitudinal axis of the first semiconductor fin.