CMOS Gate Conductor Cross-Diffusion Barrier
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Solution Overview
Problem
As semiconductor devices are scaled down, dopant diffusion between adjacent transistors becomes magnified, leading to unintended dopant concentrations in gate conductors, which can shift threshold voltages and affect the performance of n-type and p-type field effect transistors.
Innovation Solution
A diffusion barrier is sandwiched between the n-type and p-type field effect transistor gates, composed of a continuous layer of semiconductor, metal, or conductive compound, which inhibits dopant diffusion and maintains electrical continuity between the gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling is performed to reduce transistor size, then device density and integration are improved, but dopant diffusion between adjacent transistors increases causing unintended dopant concentrations in gate conductors
Solution Approach 1:
The gate conductor is segmented into multiple sections: an n-type doped region for the NFET gate, a p-type doped region for the PFET gate, and an undoped or lightly-doped intermediate section. This segmentation prevents dopant diffusion from contaminating the opposite polarity gate region, allowing device scaling while maintaining dopant concentration control.
Solution Approach 2:
An intermediate undoped or lightly-doped section is introduced between the n-type and p-type doped gate regions. This intermediate section acts as a barrier that stops dopant diffusion while allowing the gate conductor to maintain electrical continuity, thus preventing unintended dopant concentrations in scaled devices.
2Ease of manufacture
If continuous polyconductor is used for both NFET and PFET gates, then manufacturing simplicity is maintained, but dopant diffusion causes threshold voltage shifts in both transistors
Solution Approach 1:
Different sections of the gate conductor are assigned different doping characteristics: the NFET gate region receives n-type doping, the PFET gate region receives p-type doping, and the intermediate section remains undoped or lightly-doped. This local differentiation prevents threshold voltage shifts while maintaining a single continuous conductor structure for ease of manufacture.
Solution Approach 2:
The continuous gate conductor is divided into functionally distinct doped regions separated by an undoped intermediate section. This segmentation allows each region to have the appropriate doping for its function while preventing cross-contamination, thus maintaining both manufacturing simplicity and threshold voltage accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The diffusion barrier effectively blocks dopant diffusion, preventing unintended dopant concentrations and maintaining accurate threshold voltages for both n-type and p-type transistors, ensuring reliable transistor performance.
Implementation Method 1
a diffusion barrier is sandwiched between the NFET gate and the PFET gate
Implementation Method 2
a continuous layer, including at least one of a semiconductor, a metal or a conductive compound including a metal, extends continuously in the first direction over the NFET gate and the PFET gate
Data Source
AI summary
A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal.