Power Semiconductor Output Transistor Protection via Inverted Gate Discharge
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Solution Overview
Problem
Conventional power semiconductor devices fail to provide effective overcurrent protection for output MOS transistors when the voltage level of the power supply terminal drops to extremely low levels, such as ground voltage, leading to potential thermal destruction during short-circuiting events.
Innovation Solution
Incorporation of a pull-up circuit with a depression-type MOS transistor and a diode between the power supply terminal and the gate of the output MOS transistor, allowing for the discharge of electric charges on the gate when the voltage level is low, ensuring the output MOS transistor is turned off and preventing thermal destruction, and enabling the overcurrent protection circuit to operate by increasing the voltage level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional overcurrent protection circuits are used, then protection is provided under normal voltage conditions, but the protection fails when the power supply voltage drops to extremely low levels such as ground voltage
Solution Approach 1:
The patent applies inversion by reversing the conventional discharge path direction. Instead of discharging gate charges to ground, the invention discharges them to the power supply terminal. This inverted approach allows the protection circuit to function even when the power supply voltage is extremely low, because the discharge path is established relative to the power supply terminal rather than ground, enabling the MOS transistor to turn off during short-circuit conditions that would otherwise fail to trigger protection.
2Ease of operation
If the power supply voltage is extremely low, then the output MOS transistor may remain on during short-circuit, but adding conventional discharge paths to ground does not work at low voltage
Solution Approach 1:
The patent changes the reference parameter for voltage comparison by shifting from ground-referenced operation to power-supply-terminal-referenced operation. The discharge path is configured between the gate and the power supply terminal rather than ground, changing the voltage threshold condition for transistor turn-off. This parameter change allows the protection circuit to respond to overcurrent conditions across the full voltage range, including extremely low voltages near ground, by comparing against the actual power supply voltage level.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents thermal destruction of the output MOS transistor by discharging gate charges to the power supply terminal, ensuring the transistor is turned off and allowing the overcurrent protection circuit to function even at low voltage levels, thereby protecting the device from overcurrent events.
Implementation Method 1
The pull-up circuit is adapted to discharge electric charges on the gate of the output transistor, when short-circuiting of the load occurs with the voltage level on the power supply terminal lowered than the power supply voltage
Data Source
AI summary
A power semiconductor device is provided with an output transistor, a load control circuit, and a pull-up circuit. The output transistor is connected between a power supply terminal provided to receive a power supply voltage and an output terminal to be connected with a load. The load control circuit is adapted to feed the gate voltage to the gate of the output transistor. When short-circuiting of the load occurs, the load control circuit stops feeding the gate voltage to the output transistor. The pull-up circuit is connected between the power supply terminal and the gate of the output transistor. The pull-up circuit is adapted to discharge electric charges on said gate of said output transistor, when short-circuiting of the load occurs with the voltage level on the power supply terminal lowered than the power supply voltage.