Semiconductor Memory Selection Transistors with Nonuniform Threshold Voltage
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Solution Overview
Problem
The challenge in semiconductor memory devices is to achieve high integration while maintaining reliable performance, as reducing the minimum line width of fine patterns leads to deteriorated characteristics and limited integration due to photolithography process constraints.
Innovation Solution
The implementation of a transistor with a semiconductor channel region having a nonuniform threshold voltage characteristic, achieved by nonuniform doping and an L-shaped cross-section, including a first channel region segment extending opposite the sidewall and a second segment extending opposite the bottom of the gate electrode, allows for optimized threshold voltage control and minimized leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the minimum line width of fine patterns is decreased for higher integration, then the integration density is improved, but the characteristics of the fine patterns deteriorate and reliability is reduced
Solution Approach 1:
The patent applies local quality by creating nonuniform doping concentrations within the channel region. The doping concentration varies spatially, with higher doping near the drain and lower doping near the source, allowing different regions to have optimized characteristics for their specific functions while maintaining overall device reliability and integration density
Solution Approach 2:
The patent transitions from conventional planar transistors to three-dimensional vertically stacked transistors. This dimensional change allows higher integration density by utilizing the vertical space, accommodating multiple channel regions stacked above each other, thereby increasing the quantity of functional elements without proportionally increasing the footprint area
2Quantity of substance
If the minimum line width is decreased, then more memory cells can be integrated in a limited area, but the characteristics of the fine patterns deteriorate
Solution Approach 1:
The patent employs vertically stacked transistor structures that extend in the vertical dimension rather than relying solely on planar scaling. This allows more memory cells to be integrated by stacking multiple channels vertically, avoiding the need to continuously decrease minimum line width and its associated manufacturing precision challenges
Solution Approach 2:
The nonuniform doping profile is implemented to optimize local characteristics of the channel region. By varying doping concentration across different vertical and horizontal positions, the patent maintains superior fine pattern characteristics while achieving high integration through vertical stacking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration density and reliability of semiconductor memory devices by minimizing leakage current and preventing programming and reading errors, thereby improving overall device performance.
Implementation Method 1
the semiconductor channel region may be nonuniformly doped and may be configured to have an L-shaped cross-section
Implementation Method 2
The common source region, which forms a P-N rectifying junction with the semiconductor channel region, extends opposite a sidewall of the gate electrode
Data Source
AI summary
Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region.