Fin FET Liners Between Isolation and Active Areas
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Solution Overview
Problem
Current integrated circuit devices face challenges in optimizing the structure of fin field effect transistors (FETs) to achieve both high performance and integration in semiconductor devices, particularly in improving the operating accuracy and speed of highly integrated fin FETs.
Innovation Solution
The proposed integrated circuit device incorporates a fin-type active area with a dual-layered liner structure, including an insulating liner and a stress liner, which are strategically positioned between the fin-type active area and the device isolation layer, with the gate insulating layer extending to cover the channel region, liners, and device isolation layer, and featuring protrusions on the gate insulating layer to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer liner structure is used between the device isolation layer and fin-type active area, then the structure is simpler and easier to manufacture, but the carrier mobility and operating characteristics are insufficient
Solution Approach 1:
The liner structure is segmented into multiple functional layers: an insulating liner layer (first liner) and a stress liner layer (second liner). The insulating liner provides electrical isolation, while the stress liner applies mechanical stress to the channel region to enhance carrier mobility. This segmentation allows each layer to perform its specific function optimally, resolving the contradiction between structural complexity and operating characteristics.
Solution Approach 2:
The liner structure uses composite materials with different properties: the insulating liner is made of materials with high dielectric constant (e.g., silicon oxide, silicon nitride), while the stress liner is made of materials that provide tensile or compressive stress (e.g., silicon germanium, silicon carbide). This composite approach enables simultaneous achievement of electrical isolation and stress-induced carrier mobility enhancement.
2Reliability
If the gate insulating layer does not extend over the liners and device isolation layer, then the manufacturing process is simpler, but the performance and carrier mobility are reduced
Solution Approach 1:
The gate insulating layer is formed to extend in advance over the liners and device isolation layer before subsequent processing steps. This preliminary extension ensures that the gate insulating layer fully covers the channel region and adjacent structures, creating optimal electrical conditions for high carrier mobility while simplifying subsequent manufacturing steps by pre-establishing the extended coverage.
Solution Approach 2:
The gate insulating layer extends in the lateral dimension beyond the fin-type active area, covering the liners and device isolation layer. This dimensional extension creates additional coverage area that enhances the electrical characteristics and carrier mobility without requiring complex vertical stacking or additional processing dimensions.
3Productivity
If highly integrated fin FETs are implemented, then the integration density increases, but the operating accuracy and speed deteriorate
Solution Approach 1:
The patent applies local quality enhancement through the stress liner layer that is positioned specifically over the channel region of the fin-type active area. This localized stress application improves carrier mobility precisely where needed in the highly integrated structure, maintaining operating accuracy and speed despite high integration density. The insulating liner provides localized electrical isolation to prevent interference between adjacent devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the operating characteristics and performance of highly integrated fin FETs by optimizing the structure, leading to enhanced carrier mobility and optimized operating characteristics in semiconductor devices.
Implementation Method 1
a stress liner spaced apart from the fin-type active area with the insulating liner between the stress liner and the fin-type active area
Data Source
AI summary
An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.