Dummy Poly Decoupling Capacitors on STI Regions

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Solution Overview

Problem

In semiconductor integrated circuits, voltage fluctuations in power supply lines due to transient currents can cause noise and degrade noise margins, leading to reduced reliability and potential circuit malfunction, especially at high operational frequencies.

Innovation Solution

The use of dummy poly layer patterns on shallow trench isolation regions to form metal-oxide-metal decoupling capacitors, which serve a dual purpose of meeting poly-density design rules and providing fringe-type decoupling capacitance without occupying additional chip area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If decoupling capacitors are added to reduce voltage fluctuations, then noise margin stability is improved, but chip area increases

Engineering Contradiction:
Improvenoise margin stabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the decoupling capacitor function with existing dummy poly layer patterns that are already present on the shallow trench isolation regions. By merging the capacitor formation process with the existing dummy conductor structures, the patent achieves decoupling functionality without requiring additional dedicated capacitor area, thus resolving the contradiction between improving noise margin stability and minimizing chip area

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The dummy poly layer patterns serve dual purposes: they maintain poly-density design rules for manufacturing reliability and simultaneously provide fringe-type decoupling capacitance. This multi-functionality allows the same structure to address both manufacturing requirements and electrical performance requirements without consuming additional chip area

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If transient current suppression is enhanced, then voltage fluctuation reduction is improved, but circuit complexity increases

Engineering Contradiction:
Improvevoltage fluctuation reductionVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The existing dummy poly layer patterns automatically provide decoupling capacitance without requiring additional circuit elements or control mechanisms. The fringe capacitance inherent in the dummy conductor structures serves the voltage fluctuation reduction function passively, eliminating the need for active transient current suppression circuits and thereby maintaining simple circuit architecture while improving voltage stability

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces voltage fluctuations, enhances circuit reliability, and saves chip area by utilizing existing dummy conductor patterns, resulting in improved noise margin stability and area efficiency.

Implementation Method 1

Decoupling capacitors act as charge reservoirs that additionally supply currents to circuits to prevent momentary drops in supply voltage

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

first and second dummy conductive patterns formed in the same gate electrode layer over the STI region... providing fringe-type decoupling capacitance

Methodology Applied
Scientific EffectFringe capacitance: Capacitance

Data Source

PatentUS8692306B2Decoupling capacitor and method of making same
Publication Date: 2014.04.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8692306B2 patent drawing
  • US8692306B2 patent drawing
  • US8692306B2 patent drawing

AI summary

A semiconductor substrate has at least two active regions, each having at least one active device that includes a gate electrode layer, and a shallow trench isolation (STI) region between the active regions. A decoupling capacitor comprises first and second dummy conductive patterns formed in the same gate electrode layer over the STI region. The first and second dummy conductive regions are unconnected to any of the at least one active device. The first dummy conductive pattern is connected to a source of a first potential. The second dummy conductive pattern is connected to a source of a second potential. A dielectric material is provided between the first and second dummy conductive patterns.