Stacked MOSFET Current Mirror for Deep-Submicron Matching
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Solution Overview
Problem
As integrated circuit manufacturing processes scale down to deep-submicron levels (e.g., 32 nm, 20 nm, 16 nm, 7 nm, 5 nm), the limitations of metal-oxide-semiconductor field-effect transistors (MOSFETs) with long channel lengths become significant, particularly in analog circuit design, where current mismatch issues arise due to process variations, making it challenging to achieve desired performance characteristics like output resistance and current matching in current mirror circuits.
Innovation Solution
The solution involves stacking multiple transistors with short channel lengths to form equivalent transistors with long channel lengths, where transistors are connected in series with their gates tied together, allowing for the reduction of current mismatch by simulating the relationship between stage numbers and current mismatch percentages, thereby optimizing the performance of current mirror circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional long channel length MOSFETs are used in deep-submicron processes, then output resistance and current matching performance are improved, but manufacturing becomes infeasible due to process scaling limitations
Solution Approach 1:
The patent divides a single long channel length transistor into multiple short channel length transistors connected in series (stacked configuration). Each transistor in the stack has a short channel length suitable for deep-submicron processes (e.g., 5nm, 7nm, 16nm), while the series connection achieves the equivalent electrical characteristics of a long channel transistor, including high output resistance and improved current matching performance.
2Manufacturing precision
If multiple transistors are stacked in series to achieve long channel length characteristics, then current mismatch is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple short channel transistors into a unified stacked-gate structure where all transistors share a common gate connection. This merging approach maintains the current mismatch reduction benefits of multiple series-connected transistors while simplifying the control architecture by providing a single gate terminal that simultaneously controls all transistors in the stack, reducing the complexity of individual gate control circuits.
3Ease of manufacture
If short channel length transistors are used, then manufacturing in deep-submicron processes is enabled, but current mismatch and output resistance performance deteriorate
Solution Approach 1:
The patent transitions from varying channel length in a single transistor (one-dimensional approach) to varying the number of stacked transistor stages (multi-dimensional approach). By stacking multiple short channel transistors in series, the effective channel length is extended not by making each transistor longer (which would require process changes) but by adding more stages in the vertical dimension, thereby achieving long channel characteristics while maintaining compatibility with advanced deep-submicron process nodes.
Data Source
AI summary
An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.