Asymmetric Semiconducting Layer Turning Portion for Display Panel
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Solution Overview
Problem
Current display panel manufacturing faces challenges in achieving uniform resistance in semiconducting layers, leading to increased resistance differences and potential breakage during patterning, which affects the electrical characteristics and reliability of LCDs.
Innovation Solution
A semiconducting layer with a specifically designed turning portion is formed, featuring a more curving inner edge and less curving outer edge, reducing resistance differences and preventing over-etching, thereby ensuring uniform resistance and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional semiconducting layer with straight edges is used, then the manufacturing process is simple, but the resistance is non-uniform and the layer is prone to breakage during patterning
Solution Approach 1:
The patent applies asymmetry by designing the turning portion of the semiconducting layer with different curvatures for its inner and outer edges. The inner edge has a first curvature while the outer edge has a second curvature that is different from the first, creating an asymmetric geometry that optimizes electrical characteristics and reduces resistance non-uniformity without requiring complex manufacturing processes
Solution Approach 2:
The patent employs curvature by replacing sharp corners with rounded turning portions in the semiconducting layer. The inner and outer edges of the turning portion have specific curvatures that prevent stress concentration and reduce the likelihood of breakage during patterning, while also improving resistance uniformity across the layer
2Reliability
If the semiconducting layer has high resistance, then material deposition is easier, but electrical performance deteriorates
Solution Approach 1:
The patent applies local quality by optimizing the geometry of specific regions within the semiconducting layer. The turning portion is designed with particular inner and outer edge curvatures tailored to its local position, which addresses resistance non-uniformity in critical areas without requiring changes to the entire layer structure or manufacturing precision
3Productivity
If sharp corners are used in the semiconducting layer, then the patterning process is faster, but the layer breaks easily during manufacturing
Solution Approach 1:
The patent replaces sharp corners with curved turning portions in the semiconducting layer. The inner edge of the turning portion has a first curvature and the outer edge has a second curvature, which eliminates stress concentration points that would cause breakage during patterning and manufacturing, thereby improving production yield without significantly impacting patterning speed
Data Source
AI summary
An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are electrically connected and share a semiconducting layer which comprises a first lateral portion, a turning portion and a bottom portion. The turning portion connects to the first lateral portion. The bottom portion connects to the turning portion. In one embodiment, a first outer edge extending line of the first lateral portion, a second outer edge extending line of the bottom portion and a third outer edge of the turning portion defines a first region. A first inner edge extending line of the first lateral portion, a second inner edge extending line of the bottom portion and a third inner edge of the turning portion defines a second region. The area of the first region is smaller than that of the second region.