Thin-Film Transistor Doping Layout to Reduce Display Hysteresis
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Solution Overview
Problem
Existing display technologies face challenges in improving image quality, particularly in reducing afterimage effects and hysteresis, which affect the overall device characteristics and efficiency of organic light-emitting display apparatuses.
Innovation Solution
A display apparatus is designed with a substrate featuring a first thin film transistor having a source region, drain region, and channel region doped with a p-type dopant and inert gas ions, where the concentration of the inert gas ions is uniform across these regions, and a display device connected to the transistor, including an emission layer, to enhance device properties and reduce hysteresis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amorphous silicon layer is doped with p-type dopant and inert gas ions before crystallization, then device characteristics are improved and hysteresis is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines the doping process and crystallization process into a single integrated step. The amorphous silicon layer is doped with both p-type dopant and inert gas ions before crystallization, merging what would traditionally be separate manufacturing steps into one unified process, thereby improving device characteristics while managing process complexity
Solution Approach 2:
The patent uses a composite doping approach by introducing two types of dopants (p-type dopant and inert gas ions) into the amorphous silicon layer simultaneously. This composite doping strategy improves the electrical characteristics and reduces hysteresis in the thin film transistor while maintaining process efficiency
2Loss of time
If the amorphous silicon layer is doped with p-type dopant and inert gas ions before crystallization, then processing time is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs the doping action before crystallization, preparing the amorphous silicon layer with both p-type dopant and inert gas ions in advance. This preliminary doping ensures that the dopants are uniformly distributed throughout the layer before the crystallization process begins, reducing the need for subsequent doping steps and decreasing overall processing time
Solution Approach 2:
The patent changes the physical and chemical parameters of the amorphous silicon layer by introducing specific concentrations of p-type dopant and inert gas ions. By carefully controlling these doping parameters before crystallization, the patent achieves uniform dopant distribution and maintains manufacturing precision while reducing processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves image quality by reducing hysteresis and afterimage effects, while also reducing processing time and manufacturing costs through simultaneous doping and crystallization of the amorphous silicon layer, resulting in improved device characteristics.
Implementation Method 1
doping the amorphous silicon layer with a first dopant and a second dopant
Implementation Method 2
crystallizing the amorphous silicon layer
Data Source
AI summary
A display apparatus includes a substrate, a first thin film transistor on the substrate, the first thin film transistor including an active layer including a source region, a drain region, and a channel region between the source region and the drain region, and a display device on the substrate and electrically connected to the first thin film transistor. The source region, the drain region, and the channel region include a first dopant and a second dopant, the second dopant being different from the first dopant. A concentration of the first dopant in the channel region is less than a concentration of the first dopant in the source region and the drain region.