Semiconductor Device Dummy Pattern Well Bias Integration

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving operational stability and minimizing size due to the need for separate guard rings and limited space for interconnections, which restricts the reduction of device size and efficiency.

Innovation Solution

The semiconductor device utilizes an existing dummy pattern to apply a well bias voltage to transistors, eliminating the need for separate guard rings and allowing for efficient space utilization between logic array areas, thereby enhancing operational stability and reducing device size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate guard rings are used to provide well bias voltage, then operational stability is improved, but device area increases

Engineering Contradiction:
Improveoperational stabilityVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the dummy pattern (originally used for layout regularity) with the guard ring function (providing well bias voltage). By merging these two separate structures into one, the device achieves operational stability without requiring additional area for separate guard rings, thus resolving the contradiction between reliability and device area.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The dummy pattern is given multiple functions: it maintains layout regularity (original function) and simultaneously provides well bias voltage (new function). This multi-functionality eliminates the need for separate guard rings, reducing device area while maintaining operational stability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate guard rings are used to provide well bias voltage, then operational stability is improved, but interconnection space is reduced

Engineering Contradiction:
Improveoperational stabilityVSAvoidinterconnection space
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

By merging the dummy pattern with the guard ring function, the patent eliminates separate guard ring structures, thereby freeing up space that can be used for interconnections between transistors, resolving the contradiction between operational stability and interconnection space.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If dummy pattern is used for well bias voltage application, then device size is reduced, but operational stability may be compromised

Engineering Contradiction:
Improvedevice sizeVSAvoidoperational stability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The dummy pattern serves itself by providing well bias voltage to adjacent transistors. Through this self-service mechanism, the dummy pattern maintains layout regularity while simultaneously providing operational stability, thus resolving the contradiction between device size reduction and operational stability.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9842837B2Semiconductor device
Publication Date: 2017.12.12 SK HYNIX INC
  • US9842837B2 patent drawing
  • US9842837B2 patent drawing
  • US9842837B2 patent drawing

AI summary

Disclosed is a semiconductor device including a plurality of conductive patterns formed on a semiconductor substrate while being spaced apart from one another at a preset interval and extending in a first direction, and a plurality of junction areas formed by doping impurities in the semiconductor substrate and provided between the conductive patterns. The plurality of junction areas includes transistor junction areas and dummy junction areas. Each of the transistor junction areas is connected through a contact to a source/drain electrode, and the contact is formed at a higher level than the transistor junction areas. Each of the dummy junction areas is connected to a bias contact formed at higher level than the dummy junction areas. A well bias voltage is applied to the dummy junction areas through the bias contact.