Fin Gate Oxide Structure for HV Leakage and Breakdown Control
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Solution Overview
Problem
The integration of high-voltage and low-voltage devices in semiconductor processing faces challenges such as current leakage and control of breakdown voltage as device scaling decreases, requiring improved fabrication methods to enhance device performance.
Innovation Solution
A method involving the formation of fin-shaped structures on both high-voltage and low-voltage regions, followed by an oxidation process to create a gate oxide layer with bumps, and the use of shallow trench isolation and epitaxial layers to improve device performance and control voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling is decreased to integrate high-voltage and low-voltage devices, then integration density is improved, but current leakage and breakdown voltage control deteriorate
Solution Approach 1:
The substrate is divided into distinct high-voltage and low-voltage regions with separate fin-shaped structures. The gate oxide layer is segmented to directly connect only to the fin-shaped structures in each respective region, isolating the voltage control mechanisms and preventing current leakage between regions while maintaining high integration density.
Solution Approach 2:
Different regions of the substrate are given different structural qualities - the high-voltage region has fin-shaped structures with gate oxide direct connection for voltage control, while the low-voltage region has separate fin structures. This local differentiation allows each region to be optimized for its specific voltage requirements, improving reliability while maintaining integration.
2Productivity
If device scaling is decreased to integrate high-voltage and low-voltage devices, then integration density is improved, but breakdown voltage control deteriorates
Solution Approach 1:
The gate oxide layer is segmented to directly connect only to fin-shaped structures in specific high-voltage regions, creating distinct voltage control zones. This segmentation allows precise control of breakdown voltage in each region independent of the other, maintaining manufacturing precision while achieving high integration density.
Solution Approach 2:
The gate oxide layer acts as an intermediary structure that selectively connects to fin-shaped structures. By controlling where the gate oxide directly connects (only to fins in high-voltage regions), the invention mediates between the conflicting requirements of high integration density and precise breakdown voltage control.
3Reliability
If channel length is extended to reduce current leakage, then device performance is improved, but device area increases
Solution Approach 1:
The invention transitions from planar device structures to three-dimensional fin-shaped structures. By extending the channel length vertically through the fin height rather than horizontally, the device achieves longer effective channel length for current leakage control without proportionally increasing the planar device area, thus resolving the contradiction between reliability and area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively extends the channel length between the source and drain regions, reducing current leakage and improving high-voltage device performance by enhancing voltage control and power switching efficiency.
Implementation Method 1
performing an oxidation process to form a gate oxide layer on and directly connecting the first fin-shaped structures
Data Source
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AI summary
A method for fabricating a semiconductor device includes the steps of providing a substrate having a high voltage (HV) region and a low voltage (LV) region, forming first fin-shaped structures (20) on the HV region, and then performing an oxidation process to form a gate oxide layer (46) on and directly connecting the first fin-shaped structures. Preferably, a bottom surface of the gate oxide layer includes first bumps (48) on the first fin-shaped structures while a top surface of the gate oxide layer includes second bumps (50).