Multinary Memory Cells Using Binary-Weighted Capacitor Sub-Bit Units
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Solution Overview
Problem
Current binary memory devices are limited in their ability to store multiple states efficiently, which restricts their capacity for high-density data storage and computing speed.
Innovation Solution
The development of multinary memory cells that can operate with more than two states by using a parallel connection of N sub-bit units, each comprising a transistor and a capacitor, allowing for 2N possible states and enabling efficient data processing through scalable design and manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If binary memory devices are used, then device simplicity is maintained, but data storage density and computing speed are limited
Solution Approach 1:
The memory cell is segmented into N sub-bit units, where each sub-bit unit contains a transistor and capacitor. This segmentation allows the cell to store 2^N states instead of binary 2 states, achieving higher storage density while maintaining a systematic and scalable structure that doesn't exponentially increase complexity.
Solution Approach 2:
The patent transitions from binary (2 states) to multinary (2^N states) by adding an additional dimension of storage capacity through multiple sub-bit units. This dimensional expansion in state space allows exponential increase in storage density without proportionally increasing physical footprint or structural complexity.
2Quantity of substance
If multinary bit cells with N sub-bit units are implemented, then storage capacity increases to 2N states, but manufacturing complexity increases
Solution Approach 1:
By dividing the memory cell into identical, modular sub-bit units, the manufacturing process becomes repetitive and standardized. Each sub-bit unit can be manufactured using the same processes, making the overall manufacturing scalable and manageable despite the increased number of components.
Solution Approach 2:
The patent uses parameter changes in the capacitor dielectric layers (different dielectric constants or thicknesses) to differentiate between sub-bit units. This allows for systematic variation of electrical parameters during manufacturing to achieve the desired 2^N state capacity without requiring fundamentally different manufacturing processes for each unit.
3Productivity
If parallel connection of N sub-bit units is used, then computing speed is enhanced, but device complexity increases
Solution Approach 1:
The parallel connection of N sub-bit units enables simultaneous processing of multiple bits, enhancing computing speed through inherent parallelism. The segmented structure allows independent operation of each sub-bit unit while maintaining a relatively simple overall circuit configuration that can be systematically extended.
Data Source
AI summary
A memory device may include at least one multinary memory cell. Each multinary memory cell includes a parallel connection of N sub-bit units. N is an integer greater than 1. Each of the N sub-bit units includes a series connection of a respective transistor and a respective capacitor. A first sub-bit unit includes a first capacitor having a capacitance of C, and each i-th sub-unit includes an i-th capacitor having a capacitance of about 2i-1×C. A multinary bit having 2N values may be stored. A device network including multiple multinary logic units is also provided. Each of multiple multinary logic unit includes a parallel connection of N sub-bit units. Each sub-bit unit includes a series connection of a respective transistor and a respective capacitor having capacitance ratios of powers of 2.