Lattice Stack for GAA Transistor Internal Spacer Fabrication
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Solution Overview
Problem
The fabrication of gate-all-around (GAA) semiconductor devices with internal spacers poses challenges due to uneven spacing between stacked transistors, leading to parasitic capacitance and electrical shorting, particularly in stacked nanoribbon transistors.
Innovation Solution
A lattice structure with alternating thin sacrificial layers of channel material and non-channel material is used to facilitate uniform lateral etching and spacing between nanoribbons, resulting in a robust internal spacer with a crenelated or corrugated profile that provides sufficient isolation between stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for stacked nanoribbon transistors, then manufacturing simplicity is maintained, but uneven spacing between transistors occurs leading to parasitic capacitance and electrical shorting
Solution Approach 1:
The patent introduces sacrificial layers and lattice structures during the fabrication process that are removed later to create the desired spacing. This preliminary action ensures uniform spacing between nanoribbons is achieved during manufacturing, preventing electrical shorting while maintaining processability through systematic preparation steps.
Solution Approach 2:
The patent uses sacrificial layers as intermediary elements that facilitate the creation of uniform spacing. These temporary structures act as mediators during fabrication, enabling precise control of transistor spacing that would otherwise be difficult to achieve, and are subsequently removed to leave the final clean structure.
2Reliability
If internal spacers are added to prevent electrical shorting, then reliability improves, but parasitic capacitance increases due to uneven spacing
Solution Approach 1:
The patent creates locally optimized spacing through the lattice structure and sacrificial layers, ensuring that the spacing between nanoribbons is uniform in critical regions. This local quality control prevents the formation of parasitic capacitance by eliminating uneven spacing, while still providing adequate isolation for reliability.
Solution Approach 2:
The patent systematically controls the spacing parameter through the design of sacrificial layer thickness and lattice structure dimensions. By precisely adjusting these parameters, uniform spacing is achieved that simultaneously provides electrical isolation and minimizes parasitic capacitance, resolving the contradiction between reliability and harmful electromagnetic effects.
3Manufacturing precision
If uniform spacing is achieved through lattice structures with sacrificial layers, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent divides the fabrication process into segmented steps involving multiple sacrificial layers and lattice structures. This segmentation allows precise control of spacing by treating different regions and layers independently, achieving manufacturing precision through systematic division of the complex fabrication task into manageable stages.
Solution Approach 2:
The patent uses repetitive lattice structures and sacrificial layers that are copied throughout the device architecture. This copying approach standardizes the spacing control mechanism across the entire chip, achieving consistent manufacturing precision while leveraging proven process modules rather than creating entirely new complex structures.
Data Source
Figure 1A~1B
Figure 1C
Figure 2A
AI summary
Techniques are provided herein to form gate-all-around (GAA) semiconductor devices (100), such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons (104, 108) extending in the same (e.g., horizontal) direction where one device (101) is located vertically above the other device (103). An internal spacer structure (118) extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features (120) between the two devices. A gate structure (114) that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.