Semiconductor Power Rail Structure With Exposed Metal Alignment Reference
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Solution Overview
Problem
The increasing RC delay in advanced technology nodes hampers the buried power rail's ability to provide sufficient power support to standard cells in semiconductor devices, and the alignment accuracy of high-aspect-ratio vias with power rails on the back of semiconductor wafers is low, affecting device performance.
Innovation Solution
A method involving forming a power rail opening and a through-hole in the substrate, followed by depositing a first metal layer within these structures, thinning, and back-etching to expose the metal layer, which serves as both a power connection and an alignment reference for improved power distribution and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via with high aspect ratio is formed to connect to the power rail on the back of the wafer, then the power distribution structure can be formed on the back of the semiconductor wafer, but the alignment accuracy between the via and the power rail becomes low
Solution Approach 1:
The patent performs preliminary actions by forming the power rail opening and filling it with metal layer before thinning the substrate. This ensures the power rail structure is established in advance, providing a reference for subsequent alignment operations and enabling accurate connection formation.
Solution Approach 2:
The patent transitions from a planar alignment problem to a three-dimensional solution by forming the power rail opening that extends through the substrate thickness, then thinning the substrate to expose the metal layer. This dimensional approach allows alignment to be achieved through vertical exposure rather than purely lateral positioning.
2Manufacturing precision
If the substrate is thinned to expose the metal layer, then the metal layer can serve as an alignment reference, but additional processing steps are required
Solution Approach 1:
The metal layer formed in the power rail opening serves multiple functions: it provides the power connection and simultaneously acts as an alignment reference for subsequent via formation. This multi-functionality reduces the need for separate alignment markers and simplifies the overall process despite the thinning step.
Solution Approach 2:
The power rail structure itself serves as the alignment reference, eliminating the need for separate alignment markers or additional reference structures. The metal layer automatically provides the necessary alignment information for via formation, making the system self-aligning.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure including: a substrate, where the substrate includes a first region and a second region adjacent to the first region; a plurality of fins formed over the first region of the substrate; an isolation layer over the substrate between adjacent fins of the plurality of fins, where a top of the isolation layer is lower than a top surface of a fin of the plurality of fins, the isolation layer over the second region and the second region of the substrate together contain a power rail opening, and the substrate contains a through-hole at a bottom of the power rail opening; and a first metal layer in the power rail opening and the through-hole, where a back surface of the first metal layer is above a back surface of the substrate.