Vertical Pin-Type Capacitor for Image Sensors

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Solution Overview

Problem

Current image sensing devices face challenges in achieving high capacitance per unit area, which is essential for enhancing the performance of image sensors in various applications such as digital cameras and surveillance systems.

Innovation Solution

The implementation of a vertical pin-type capacitor with a recessed structure and junctions in an active region, where impurity regions and insulation layers are strategically arranged to increase capacitance, allowing for efficient charge storage and signal processing in image sensing devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional capacitor structures are used, then device area is reduced, but capacitance per unit area is insufficient

Engineering Contradiction:
Improvecapacitance per unit areaVSAvoiddevice area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar capacitor structure to a vertical three-dimensional structure by forming a trench in the substrate and filling it with conductive and insulation layers. This vertical configuration increases the effective capacitance area without occupying additional horizontal device area, directly resolving the contradiction between achieving high capacitance per unit area and maintaining compact device footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds the capacitor structure within the substrate by forming a trench and filling it with nested layers of conductive material and insulation material. This nested configuration allows the capacitor to be integrated within the existing device architecture, increasing capacitance density without expanding the overall device area.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If capacitor size is increased to achieve higher capacitance, then charge storage capacity improves, but device area increases

Engineering Contradiction:
Improvecharge storage capacityVSAvoiddevice area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent achieves increased charge storage capacity by extending the capacitor structure vertically through the substrate depth rather than horizontally across the device area. The trench depth and vertical layering provide additional capacitance volume without increasing the horizontal footprint, resolving the contradiction between charge storage capacity and device area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances capacitance per unit area, leading to improved performance and efficiency in image sensing devices by effectively storing electric charges and processing pixel signals, thereby addressing the limitations of existing technologies.

Implementation Method 1

a capacitor located adjacent to the logic circuits. The capacitor may include an active region, a recessed structure, and a first junction

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11152408B2Vertical pin-type capacitor and image sensing device including the same
Publication Date: 2021.10.19 SK HYNIX INC
  • US11152408B2 patent drawing
  • US11152408B2 patent drawing
  • US11152408B2 patent drawing

AI summary

An image sensing device is provided to include a pixel region and a peripheral region located outside of the pixel region. The peripheral region includes logic circuits located to receive a pixel signals from the pixel region and configured to process the pixel signals and a capacitor located adjacent to the logic circuits. The capacitor includes an active region, a recessed structure, and a first junction. The active region includes a first impurity region and a second impurity region formed over the first impurity region. The recessed structure is at least partly disposed in the active region and including a first portion disposed in the active region and including a conductive material and a second portion surrounding the first portion and including an insulation material. The first junction is formed in the active region and spaced apart from the recessed structure by a predetermined distance.