MOS Gate Self-Protection via Base Layer Charge Dissipation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Integrated circuits with MOS and bipolar devices face plasma-induced damage during gate conductor patterning, leading to degraded dielectric breakdown voltage and reliability issues, as existing protective methods require additional process steps and masking.

Innovation Solution

A method where a dielectric layer is deposited over a semiconductor layer with defined electrically active and inactive regions, and a base layer is used to connect the MOS gate region with the semiconductor layer, allowing charge dissipation and providing self-protection against plasma-induced damage without adding extra process steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a protective diode is formed directly connected to the gate electrode before patterning, then plasma charging damage is protected against, but additional masking and implant steps are required

Engineering Contradiction:
Improveprotection against plasma charging damageVSAvoidadditional masking and implant steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The base layer is formed in advance during the bipolar base definition step, before gate patterning occurs. This preliminary formation of the charge dissipation path eliminates the need for additional protective structures during subsequent gate processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The base layer serves dual functions: it acts as the bipolar transistor base region and simultaneously provides a charge dissipation path for gate protection. This multi-functionality eliminates the need for separate protective structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Ease of manufacture

If the gate conductor is patterned during final stages, then device functionality is achieved, but plasma induced damage degrades dielectric breakdown voltage

Engineering Contradiction:
Improvegate conductor patterningVSAvoiddielectric breakdown voltage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The base layer acts as an intermediary charge dissipation path between the gate conductor and the semiconductor substrate. It provides a controlled route for charge carriers to flow, protecting the gate oxide from high electric fields during plasma processing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The base layer automatically provides charge dissipation functionality without requiring additional protective structures or process steps. The same base layer formed for bipolar device operation serves the dual purpose of gate protection.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively protects against plasma-induced damage during gate conductor patterning without increasing production costs or complexity, ensuring reliable operation of integrated circuits by dissipating charge carriers through the semiconductor layer.

Implementation Method 1

the charge carriers which accumulate in the gate region can be dissipated via the base layer into the semiconductor layer

Methodology Applied
Scientific EffectCharge carrier dissipation: Conduction (electrical)

Implementation Method 2

The plasma used in a plasma process step is able to electrically charge an electrically conductive supply conductor to a gate region of a field-effect transistor and to electrically charge the gate region

Methodology Applied
Scientific EffectPlasma charging: Plasma

Data Source

PatentUS8294218B2Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection
Publication Date: 2012.10.23 TEXAS INSTRUMENTS INC
  • US8294218B2 patent drawing
  • US8294218B2 patent drawing
  • US8294218B2 patent drawing

AI summary

An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.