VFET Source/Drain Notch Isolation for Lower Parasitic Capacitance

Solution Overview

Problem

Vertical field effect transistors (VFETs) face issues with increased N-to-P isolation leakage and parasitic capacitance due to the configuration of the active area, which affects the performance and scalability of semiconductor devices beyond the 7 nm node.

Innovation Solution

The method involves forming a notched region in the source/drain layer beneath the gate structure and filling it with a dielectric material to reduce parasitic capacitance by self-aligned active area edge epi isolation, thereby improving the isolation between the source/drain and gate layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the active area configuration is used in vertical field effect transistors, then device density and scaling are improved, but parasitic capacitance and isolation leakage increase

Engineering Contradiction:

Improvedevice densityVSAvoidparasitic capacitance

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The source/drain layer is segmented by creating notched regions that divide it into isolated sections. These notches physically separate the source and drain regions, reducing the parasitic capacitance between them while maintaining the high-density vertical architecture. The segmentation allows each region to be independently controlled and isolated.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A dielectric material is introduced as an intermediary substance within the notched regions of the source/drain layer. This dielectric acts as a mediator that electrically isolates the source and drain regions, reducing parasitic capacitance and leakage currents while allowing the vertical FET structure to maintain its high-density configuration.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If the active area configuration is used in vertical field effect transistors, then device density and scaling are improved, but isolation leakage increases

Engineering Contradiction:

Improvedevice densityVSAvoidisolation leakage

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The source/drain layer is segmented by creating notched regions that divide it into isolated sections. These notches physically separate the source and drain regions, reducing the parasitic capacitance between them while maintaining the high-density vertical architecture. The segmentation allows each region to be independently controlled and isolated.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A dielectric material is introduced as an intermediary substance within the notched regions of the source/drain layer. This dielectric acts as a mediator that electrically isolates the source and drain regions, reducing parasitic capacitance and leakage currents while allowing the vertical FET structure to maintain its high-density configuration.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If source/drain regions are placed at ends of fin channels, then vertical transport architecture is achieved, but parasitic capacitance between source/drain and gate increases

Engineering Contradiction:

Improvevertical transport architectureVSAvoidparasitic capacitance

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The source/drain layer is segmented by creating notched regions that divide it into isolated sections. These notches physically separate the source and drain regions, reducing the parasitic capacitance between them while maintaining the high-density vertical architecture. The segmentation allows each region to be independently controlled and isolated.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A dielectric material is introduced as an intermediary substance within the notched regions of the source/drain layer. This dielectric acts as a mediator that electrically isolates the source and drain regions, reducing parasitic capacitance and leakage currents while allowing the vertical FET structure to maintain its high-density configuration.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11742246B2Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors

Publication Date: 2023.08.29 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.