FinFET Via Air-Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As feature size continues to shrink and integration density increases in semiconductor devices, parasitic capacitance significantly rises, leading to decreased performance in FinFET devices.
Innovation Solution
The formation of air gaps around vias and in the dielectric layer of FinFET devices reduces parasitic capacitance by lowering the dielectric constant of the interlayer dielectric layers, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is reduced to increase integration density, then integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent introduces air gaps (porous structures) into the interlayer dielectric layers surrounding vias and fins. Air has a dielectric constant of approximately 1, significantly lower than conventional dielectric materials (k=3-10), thereby reducing parasitic capacitance while maintaining integration density. The air gaps are formed by removing portions of the dielectric material, creating a porous or hollow structure that reduces harmful capacitive coupling.
Solution Approach 2:
The patent extracts (removes) portions of the interlayer dielectric material to create air gaps around vias and fins. This extraction eliminates the dielectric material that would otherwise contribute to parasitic capacitance, replacing it with air or vacuum. The removed dielectric material is completely taken out from the system, leaving voids that reduce capacitive coupling between adjacent conductive structures.
2Object-generated harmful factors
If air gaps are formed to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the air gaps at strategic locations (around vias and fins) during the manufacturing process. The dielectric material is removed in advance to create air gaps before subsequent processing steps. This preliminary creation of air gaps ensures that parasitic capacitance is reduced from the outset, and the structure is maintained through subsequent manufacturing steps without requiring additional complex interventions.
Solution Approach 2:
The patent applies local quality by introducing air gaps only in specific locations where parasitic capacitance is most problematic (around vias and fins), rather than uniformly throughout the entire device. This localized approach reduces parasitic capacitance where it matters most while minimizing the overall structural complexity and material removal required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and enhances the performance of FinFET devices with minimal additional cost, easily integratable into existing manufacturing flows.
Implementation Method 1
parasitic capacitance by lowering the dielectric constant of the interlayer dielectric layers
Data Source
AI summary
A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.