Display Pixel Layout for Parasitic Capacitance Reduction

The patent introduces a new spatial dimension by placing conductive electrodes at different positions relative to scanning lines (first position for first pixels, second position for second pixels). This dimensional arrangement optimizes the overlap area between conductive electrodes and scanning lines, thereby reducing parasitic capacitance without compromising pixel resolution or display quality.

The patent applies different structural configurations to different pixel types (first pixels versus second pixels). Specifically, first pixels have conductive electrodes at a first position with a first overlap area, while second pixels have conductive electrodes at a second position with a second overlap area. This localized differentiation allows optimization of parasitic capacitance reduction in specific regions while maintaining overall display performance.

The light shielding film is selectively applied only to specific regions where conductive electrodes overlap with scanning lines or common electrodes, rather than covering the entire pixel area. This localized shielding approach reduces parasitic capacitance in critical areas while preserving the aperture ratio in light-emitting regions, thus resolving the contradiction between capacitance reduction and maintaining display brightness.

The pixel structure is segmented into different functional zones: regions with light shielding film for parasitic capacitance reduction and regions without shielding for light emission. This segmentation allows the light shielding film to be positioned strategically to reduce capacitance without compromising the aperture ratio in the light-emitting areas.