Gate Cut Structure Sequencing for Source/Drain Integrity
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Solution Overview
Problem
The challenge in forming semiconductor devices lies in the interference of gate cut structures with existing source or drain regions during the fabrication process, particularly due to etching processes that can adversely affect the integrity of these regions.
Innovation Solution
The solution involves forming epitaxial source or drain regions after the gate cut structures are formed, using sacrificial fill material in the source/drain trenches, and then removing the sacrificial fill material to prevent interference and ensure the integrity of the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate cut structures are formed before source or drain regions, then gate structure formation is simplified, but the etching process adversely affects the integrity of source or drain regions
Solution Approach 1:
The gate cut structure is formed preliminarily before the source or drain regions are created. The gate cut structure includes a dielectric material that extends through the gate structure, preparing the gate region in advance. This preliminary formation simplifies the overall gate structure fabrication process while the subsequent selective epitaxial growth ensures source or drain region integrity is maintained.
Solution Approach 2:
Sacrificial fill material is used as an intermediary substance during the formation process. The sacrificial fill material temporarily occupies the source/drain trenches during gate cut structure formation, protecting the future source or drain regions from etching damage. After the gate cut structure is formed, the sacrificial fill material is removed, allowing clean epitaxial growth of source or drain regions without adverse etching effects.
2Reliability
If source or drain regions are formed before gate cut structures, then source or drain region integrity is maintained, but the fabrication process complexity increases
Solution Approach 1:
The gate cut structure is formed preliminarily with sacrificial fill material in place, which protects the source/drain trench areas during gate structure formation. This preliminary setup with sacrificial material allows subsequent source or drain region formation to proceed without complexity, as the sacrificial material is simply removed and replaced with epitaxial growth.
Solution Approach 2:
The fabrication sequence is optimized by changing the temporal parameters of when structures are formed. By forming the gate cut structure with sacrificial fill material first, then removing the sacrificial material and forming source or drain regions through epitaxial growth, the process achieves simplicity while maintaining integrity. The parameter change involves the timing and state of material presence during different fabrication stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of gate cut structures without adversely impacting the source or drain regions, maintaining their integrity and enabling precise control over the growth pattern, thereby improving the overall semiconductor device fabrication process.
Implementation Method 1
a dielectric liner on at least a sidewall and/or top surface the source or drain regions also extends up a sidewall surface of the gate cut structure
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
Techniques are provided herein to form semiconductor devices having gate cut structures. Adjacent semiconductor devices having semiconductor regions (e.g., fins or nanoribbons) extending in a first direction have a gate structure that extends over the semiconductor regions in a second direction and are separated by a gate cut structure extending in the first direction and interrupting the gate structure. The gate cut structure further extends between adjacent source or drain regions (corresponding to the adjacent semiconductor devices). A dielectric liner on at least a sidewall and/or top surface of the source or drain regions and also extends up a sidewall surface of the gate cut structure. In some cases, the gate structure includes a gate dielectric present on the semiconductor regions, but not present on the gate cut structure. A contact may pass through the liner and at least partially land on a source or drain region.