Non-volatile Memory Cell Segmentation for High-Voltage Protection
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Solution Overview
Problem
As geometries shrink in user-programmable devices like FPGAs, the maximum voltages that transistors can withstand also decrease, creating a mismatch between programming and erase voltages for non-volatile memory transistors, which poses a challenge in protecting logic circuitry from programming and erase potentials.
Innovation Solution
A non-volatile programmable memory cell is designed with a non-volatile MOS transistor in series with a volatile MOS transistor, isolated in separate wells, allowing the use of low-voltage devices and incorporating a switch to manage programming and erase operations, thereby protecting the logic circuitry from high voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory transistors use high programming and erase voltages, then programming and erase operations can be performed, but the logic circuitry is exposed to harmful high voltages that exceed the maximum voltages the transistors can withstand
Solution Approach 1:
The memory cell is divided into separate wells: a first well containing the non-volatile memory transistor and a second well containing the logic circuitry. This segmentation isolates the high-voltage programming and erase operations in the first well from the low-voltage logic circuitry in the second well, allowing high-voltage operations without exposing the logic circuitry to harmful voltages
Solution Approach 2:
An n-well acts as an intermediary structure between the non-volatile memory transistor and the logic circuitry. The n-well provides electrical isolation and protects the logic circuitry from high programming and erase voltages applied to the non-volatile memory transistor, enabling safe high-voltage operations
2Area of moving object
If transistor geometries are shrunk to increase density, then device capacity increases, but the maximum voltages the transistors can withstand decrease
Solution Approach 1:
The device is segmented into separate wells with different voltage domains. The first well accommodates the non-volatile memory transistor requiring high programming and erase voltages, while the second well contains the logic circuitry operating at low voltages. This allows small-geometry transistors in the logic circuitry to operate safely at low voltages while the memory transistor handles high-voltage operations
Solution Approach 2:
The patent changes the voltage parameter distribution across different parts of the device. By isolating high-voltage operations to the non-volatile memory transistor in the first well and maintaining low-voltage operation in the logic circuitry in the second well, the patent enables the use of small-geometry transistors that can only withstand low voltages, while still achieving high-density integration
Data Source
AI summary
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.