Polysilicon Resistor Tank Structure for Semiconductor Fabrication

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional methods for integrating metal gate transistors with polysilicon resistors face issues such as lateral over-etching and conductive residue due to height differences in hard masks, which affect the integrity and performance of semiconductor devices.

Innovation Solution

The method involves forming a tank in the shallow trench isolation (STI) of the resistor region and implanting boron atoms into the polysilicon layer to create differential etching selectivity, ensuring the polysilicon resistor and metal gate are even and reducing over-etching and residue issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional methods are used to integrate metal gate transistor with polysilicon resistor, then the fabrication process is simple, but lateral over-etching and conductive residue occur due to height differences in hard masks

Engineering Contradiction:
Improveetching precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces a vertical dimension solution by forming a tank structure (a recess or cavity) in the STI layer. This dimensional change allows the polysilicon resistor to be formed at a different height level, specifically within the tank region, thereby compensating for the height difference between the metal gate transistor and polysilicon resistor hard masks. This resolves the lateral over-etching issue by providing a structural foundation that equalizes the etching reference planes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies local quality by creating a tank structure specifically in the STI layer at the resistor region, rather than uniformly modifying the entire structure. This localized modification allows the polysilicon resistor to be formed with proper height alignment only where needed (in the tank region), while leaving other regions unchanged. The tank provides localized height compensation to prevent over-etching and residue formation at the resistor contacts.

Inventive Principle:
Principle #3Local quality

2Reliability

If height differences in hard masks are not compensated, then the fabrication process is simple, but lateral over-etching and conductive residue occur

Engineering Contradiction:
Improvedevice integrityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The tank structure introduces a vertical dimension solution by creating a recess in the STI layer. This allows the polysilicon resistor to be positioned at a different height level, specifically lower than the surrounding STI surface, thereby compensating for the height difference between the metal gate transistor and polysilicon resistor hard masks. This resolves the lateral over-etching issue by providing a structural foundation that equalizes the etching reference planes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent applies local quality by creating a tank structure specifically in the STI layer at the resistor region, rather than uniformly modifying the entire structure. This localized modification allows the polysilicon resistor to be formed with proper height alignment only where needed (in the tank region), while leaving other regions unchanged. The tank provides localized height compensation to prevent over-etching and residue formation at the resistor contacts.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the integration of metal gate transistors and polysilicon resistors by eliminating lateral over-etching and conductive residue, enhancing the reliability and performance of semiconductor devices.

Implementation Method 1

implanting boron atoms into the polysilicon layer to create differential etching selectivity

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS8940600B2Method for fabricating semiconductor device
Publication Date: 2015.01.27 MARLIN SEMICON LTD
  • US8940600B2 patent drawing
  • US8940600B2 patent drawing
  • US8940600B2 patent drawing

AI summary

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the resistor region of the substrate; forming a tank in the STI; and forming a resistor in the tank and on two sides of the top surface of the STI outside the tank.