Vertical Junction FET with All-Around Gate for Low Voltage Operation
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Solution Overview
Problem
There is a need for junction field-effect transistors (FETs) that provide low noise and high input impedance while operating at relatively low voltages, which is essential for emerging mobile and Internet of Things (IoT) applications and analog implementations of neural networks.
Innovation Solution
The development of a vertical junction FET with an all-around junction gate structure, where the gate region is formed on multiple sides of the channel region, reducing the voltage required to control current flow and enabling low-power, low-voltage operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional single-side gate structure is used, then the device structure is simpler, but the voltage requirement is higher
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a vertical three-dimensional gate structure. The gate is positioned on multiple sides of the channel region, utilizing the vertical dimension to achieve better control. This dimensional change allows the gate to control current flow from multiple directions, effectively reducing the voltage requirement by approximately half compared to single-side gate structures.
Solution Approach 2:
The gate structure is segmented into multiple regions positioned on different sides of the channel (first gate region, second gate region, and optionally third gate region). Each gate segment independently controls a portion of the channel, allowing distributed control that reduces the overall voltage requirement while maintaining manageable structural complexity.
2Ease of operation
If the gate region is positioned on multiple sides of the channel, then the voltage control efficiency is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning actions during fabrication to define the multi-sided gate structure. Sacrificial layers are deposited and patterned in advance to guide the formation of the gate regions on multiple sides of the channel. This preliminary structuring simplifies subsequent manufacturing steps by providing pre-defined templates for gate formation.
Solution Approach 2:
Sacrificial layers serve as intermediary structures during fabrication. These temporary layers are deposited, patterned, and used to define the gate regions, then removed after the gate material is formed. This intermediary approach enables complex multi-sided gate structures to be manufactured using standard fabrication processes without requiring direct complex patterning.
Data Source
AI summary
A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.