Oxide Semiconductor Top-Gate TFT Layout for Lower Signal Delay
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Solution Overview
Problem
Inverted staggered transistors used in display devices suffer from signal delay due to parasitic capacitance and occupy more area, which degrades image quality, especially in large-sized or high-resolution displays, and there is a need for a planar transistor with stable semiconductor characteristics and high reliability.
Innovation Solution
A semiconductor device with a planar type top-gate structure oxide semiconductor transistor, where impurity elements like hydrogen, boron, or rare gases are introduced in regions not overlapping with the gate, source, and drain electrodes, reducing parasitic resistance and increasing on-state current while maintaining low off-state current and small area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted staggered transistor structure is used, then the manufacturing process is simple and cost is low, but signal delay increases due to parasitic capacitance between gate and source/drain electrodes
Solution Approach 1:
The patent inverts the conventional transistor structure by placing the gate electrode at the top instead of the bottom, creating a top-gate planar transistor. This inversion eliminates the overlap between gate and source/drain electrodes, thereby reducing parasitic capacitance and signal delay while maintaining manufacturing simplicity through established top-gate fabrication processes
2Ease of manufacture
If an inverted staggered transistor structure is used, then manufacturing cost is low, but the occupation area is larger than planar transistor
Solution Approach 1:
By inverting to a top-gate planar structure, the source/drain electrodes can be positioned adjacent to each other without requiring the vertical stacking space needed in inverted staggered transistors. This reduces the overall footprint and occupation area while maintaining compatibility with cost-effective fabrication processes
3Area of moving object
If a planar transistor structure is used, then the occupation area is smaller, but stable semiconductor characteristics and high reliability are not achieved
Solution Approach 1:
The patent applies local quality by creating a planar structure with a flat semiconductor layer and positioning electrodes in specific regions. The top-gate configuration provides uniform electric field distribution across the channel, ensuring stable semiconductor characteristics and high reliability while maintaining compact area occupation
Solution Approach 2:
The invention changes the structural parameters by adopting a top-gate planar configuration instead of inverted staggered. This parameter change optimizes the electric field distribution and carrier transport, achieving both compact area occupation and stable semiconductor characteristics with high reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a semiconductor device with high on-state current, low off-state current, stable electrical characteristics, and high reliability, reducing signal delay and display unevenness in large-sized or high-resolution displays while minimizing area occupation.
Implementation Method 1
impurity elements like hydrogen, boron, or rare gases are introduced in regions not overlapping with the gate, source, and drain electrodes, reducing parasitic resistance and increasing on-state current
Data Source
AI summary
A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.