Array Substrate With Suspended Semiconductor Layer For Low Off-State Current
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Solution Overview
Problem
Conventional metallic oxide TFTs face challenges in maintaining voltage across pixels at low refresh rates due to high Off-state current, which affects power consumption and display performance.
Innovation Solution
The design of an array substrate with increased distance between source and drain electrodes, along with specific semiconductor layer shapes and connection regions, increases resistance and reduces Off-state current, allowing voltage maintenance at low refresh rates while reducing TFT size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the distance between source and drain electrodes is increased to reduce Off-state current, then power consumption is reduced and voltage maintenance is improved, but device area increases
Solution Approach 1:
The semiconductor layer is designed with a three-dimensional structure including suspended regions that extend vertically from the substrate. This vertical dimension allows the current path to be lengthened without proportionally increasing the planar area, effectively reducing Off-state current while minimizing the footprint of the device.
Solution Approach 2:
The semiconductor layer incorporates curved and suspended configurations rather than straight linear paths. The suspended semiconductor layer creates a longer tortuous path for current flow between source and drain, increasing resistance and reducing leakage current without requiring a larger device area.
2Reliability
If the semiconductor layer is designed with suspended regions to increase resistance, then Off-state current is reduced, but manufacturing complexity increases
Solution Approach 1:
The semiconductor layer is divided into multiple segments including suspended regions, contact regions, and channel regions. This segmentation allows each portion to be optimized independently for its specific function while maintaining overall device performance and enabling standardized manufacturing processes.
Solution Approach 2:
The suspended semiconductor layer structure serves multiple functions simultaneously: it increases the current path length to reduce leakage, provides mechanical support, defines the active channel region, and facilitates gate control. This multi-functionality reduces the need for additional separate components and simplifies the overall device architecture.
3Speed
If the semiconductor layer configuration is optimized to reduce parasitic capacitance, then switching speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The semiconductor layer has different structural characteristics in different regions: suspended regions with larger gaps from the substrate for reduced capacitance, contact regions for electrical connection, and channel regions for current flow. Each region is locally optimized for its specific function, allowing high switching speed while using standard manufacturing tolerances.
Data Source
AI summary
An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode. A length of a shortest distance on the semiconductor layer from the first connection point to the second connection point may be no less than a reference distance which refers to a longest distance of a straight line between any two points among all points on a perimeter of the gate electrode.