Semiconductor Device Wiring for Planar Dimension Reduction
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Solution Overview
Problem
The challenge in downsizing semiconductor devices is exacerbated by the need to increase the planar dimension due to staggered bonding pads and the width of power supply wiring, which affects current density and terminal density.
Innovation Solution
The implementation of a configuration where the first and second power supply wiring pass over protective elements on the semiconductor substrate, with a pulling-out region between them, allowing the wiring to be electrically connected to a conductive layer for the bonding pads, thereby reducing the planar dimension of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bonding pads are staggered to increase terminal density, then more bonding pads can be formed for the same device size, but the planar dimension must be increased to accommodate the outer peripheral bonding pads
Solution Approach 1:
The patent applies dimensionality change by routing the first wiring vertically through multiple wiring layers (from first wiring layer through fourth wiring layer) to connect bonding pads at different peripheral positions. This three-dimensional wiring approach allows the device to accommodate staggered bonding pads without increasing planar dimension, as connections are established in the vertical dimension rather than requiring additional horizontal space.
2Ease of manufacture
If power supply wiring is arranged through a detour around the input/output circuit, then the wiring can connect power supply to bonding pads, but the wiring width is reduced which decreases current density
Solution Approach 1:
The patent segments the power supply wiring into multiple separate wiring layers (first power supply wiring in third wiring layer, second power supply wiring in fourth wiring layer). This segmentation allows each wiring segment to be independently routed with sufficient width to maintain current density, while collectively providing the necessary power supply connections to multiple bonding pads through the vertical stacking of wiring layers.
Solution Approach 2:
The patent resolves the current density issue by moving power supply wirings to different vertical layers (third and fourth wiring layers) where they can maintain adequate width without conflicting with input/output circuits in horizontal plane. This vertical separation in the z-dimension allows power wirings to detour around I/O circuits while preserving sufficient cross-sectional area for high current density.
3Reliability
If power supply wiring width is increased to maintain current density, then current density is maintained, but the planar dimension increases
Solution Approach 1:
The patent eliminates the need to increase planar dimension by utilizing the vertical dimension for power supply wirings. The first and second power supply wirings are positioned in different wiring layers (third and fourth layers respectively), allowing them to provide sufficient current-carrying capacity through increased vertical separation and layered routing rather than requiring increased horizontal width that would expand the device footprint.
Data Source
AI summary
The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.