Non-volatile Memory Control Gate Multilayer Structure
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Solution Overview
Problem
Conventional flash memory devices face issues with voids and seams in the control gate pattern due to high aspect ratios of field recesses, leading to reduced coupling ratios and deteriorated electric characteristics, especially after heat treatment which causes silicon migration and depletion fields.
Innovation Solution
The implementation of a control gate structure with a first conductive pattern that crystallizes at a higher temperature and a second conductive pattern doped with impurities, which crystallizes at a lower temperature, reduces silicon migration and void/seam defects by using a multilayer dielectric structure and specific deposition and heating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the field recess width is reduced to increase integration density, then more memory cells can be packed, but voids and seams form in the control gate pattern during deposition
Solution Approach 1:
The control gate pattern is segmented into multiple conductive layers deposited at different times and conditions. This allows each layer to be optimized for gap-filling in the narrow field recess, preventing voids and seams while maintaining high integration density.
Solution Approach 2:
A preliminary conductive layer is deposited first to fill the field recess before subsequent control gate layers are formed. This preliminary action ensures that the recess is properly filled, preventing voids and seams in the final control gate pattern.
2Reliability
If heat treatment is applied to reduce control gate resistance, then electrical conductivity is improved, but silicon migration occurs creating depletion fields and defects
Solution Approach 1:
The heat treatment parameters are optimized to achieve the desired reduction in control gate resistance while staying below the threshold temperature that causes silicon migration. This parameter adjustment allows electrical conductivity improvement without creating depletion fields or defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces void and seam defects in the control gate pattern, enhancing the operational reliability of non-volatile memory devices by maintaining improved electric characteristics despite high aspect ratios of field recesses.
Implementation Method 1
a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range
Implementation Method 2
Such an oxide/nitride/oxide dielectric layer (hereinafter, referred to as ONO layer) has a dielectric constant that is larger than the dielectric constant of a thermal oxide layer
Implementation Method 3
electrons may be either pushed into or pulled out of the floating gate pattern via a Fowler-Nordheim (F-N) tunneling mechanism
Data Source
AI summary
A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.