Hybrid Pillar Bottom Electrode Fabrication for DRAM

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Semiconductor devices with high aspect ratio bottom electrodes are prone to damage during fabrication processes, affecting the reliability and capacitance of memory devices like DRAM.

Innovation Solution

A method for fabricating a semiconductor device with a hybrid pillar-type bottom electrode, involving the formation of a mold stack pattern, a bottom electrode layer, and a supporter layer, where a barrier portion is used as an etch barrier to protect the electrode and enable selective removal, resulting in a stable capacitor structure with enhanced structural stability and capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a high aspect ratio bottom electrode is formed, then the capacitance increases, but the electrode becomes vulnerable to damage during fabrication

Engineering Contradiction:

ImprovecapacitanceVSAvoiddamage susceptibility

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The supporter layer acts as a protective intermediary that shields the high aspect ratio bottom electrode from mechanical damage during fabrication. It provides structural reinforcement without interfering with the electrode's capacitance function

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The supporter layer is prepared in advance to cushion and protect the bottom electrode from potential damage during subsequent processing steps, allowing the high aspect ratio structure to be maintained without excessive vulnerability

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the structural stability and capacitance of semiconductor devices by protecting the high aspect ratio bottom electrodes from damage and ensuring reliable fabrication, leading to improved performance in memory devices.

Implementation Method 1

forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer

Methodology Applied

Scientific EffectEtch barrier:

Implementation Method 2

The second bottom electrode layer may include a material having an etch selectivity with respect to the supporter layer

Methodology Applied

Scientific EffectEtch selectivity:

Implementation Method 3

The first bottom electrode layer and the second bottom electrode layer may have different selectivities for a chemical mechanical polishing (CMP) process

Methodology Applied

Scientific EffectCMP selectivity:

Data Source

PatentUS11322501B2Semiconductor device and method for fabricating the same

Publication Date: 2022.05.03 SK HYNIX INC

AI summary

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.