TFT Substrate Data Signal Supply Lines
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Solution Overview
Problem
The existing thin film transistor (TFT) substrates for liquid crystal displays (LCDs) face challenges in reducing size due to the need for maintaining a minimum gap between signal lines to prevent signal interference and short circuits, which increases the non-display area and substrate size.
Innovation Solution
The TFT substrate is designed with data signal supply lines formed using first and second conductive layers of different metals, and bridge electrodes connecting these lines, allowing for reduced spacing between signal lines while equalizing resistance through varying contact hole sizes, thereby reducing the substrate size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gap between neighboring signal lines is maintained to be about 4 μm to prevent signal interference and short circuits, then signal integrity is improved, but the size of the non-display area and TFT substrate increases
Solution Approach 1:
The patent transitions from planar signal line arrangement to three-dimensional stacked conductive layers. Data signal supply lines are formed in different metal layers (first conductive layer and second conductive layer) vertically stacked above each other, allowing signal transmission in the vertical dimension rather than requiring increased horizontal spacing. This layering approach reduces the horizontal gap requirements between signal lines while maintaining signal integrity.
Solution Approach 2:
Bridge electrodes are introduced as intermediary components to connect the data signal supply lines in different conductive layers to the data lines. These bridge electrodes facilitate electrical connection between layers while allowing compact horizontal spacing, as they serve as localized connection points rather than requiring extended gap distances between parallel signal lines.
2Area of stationary object
If different metal lines are used to construct data signal supply lines, then the spacing between signal lines can be reduced, but the manufacturing process complexity increases
Solution Approach 1:
The signal transmission path is segmented into multiple functional components distributed across different conductive layers: data signal supply lines in the first conductive layer, additional signal paths in the second conductive layer, bridge electrodes for inter-layer connection, and contact holes for vertical access. This segmentation allows each component to be optimized independently while reducing overall substrate size through compact vertical stacking.
Solution Approach 2:
The patent employs composite conductive structures using different metal materials for different conductive layers. The first and second conductive layers are formed with different metal compositions, allowing optimization of each layer for specific electrical characteristics while enabling reduced spacing through complementary material properties. This composite approach balances manufacturing complexity with size reduction benefits.
3Reliability
If the resistance ratio between data line and data signal supply line is equalized by varying contact hole sizes, then voltage distribution is optimized, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality variation by making contact holes of different sizes at different locations to compensate for resistance differences. Specifically, contact holes connected to the data line have different areas than those connected to the data signal supply line, creating localized resistance adjustments. This local modification optimizes voltage distribution without requiring global process changes, balancing precision requirements with performance optimization.
Data Source
AI summary
A thin film transistor substrate and fabricating method thereof by which the size of the thin film transistor substrate is reduced by constructing data signal supply lines, each of which supplies a pixel data voltage to a data line, with different metal lines, respectively includes gate and data lines crossing each other on a substrate, with a gate insulating layer disposed therebetween, a thin film transistor formed on each intersection between the gate and data lines, a display area on which a pixel electrode connected to the thin film transistor is formed, a first data signal supply line comprising a first conductive layer connected to the data line in a non-display area located at a periphery of the display area, and a second data signal supply line alternating with the first data signal supply line, with the gate insulating layer disposed therebetween, the second data signal supply line comprising a second conductive layer connected to the data line.