GAA Nanosheet Gate Structure With Uniform Electrode Height Control
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases with the scaling down and high integration density of semiconductor devices, making it challenging to achieve uniformity and efficiency in forming gate structures for transistors across regions of varying critical dimensions.
Innovation Solution
The method involves forming gate all around (GAA) transistors using a sacrificial layer and spacers, with a high-k dielectric layer and metallic layers conformally covering and wrapping around semiconductor nanosheets, and employing a metal oxide masking layer to ensure uniform etching and patterning across regions of different widths, allowing for precise control of gate electrode heights and minimizing damage during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional manufacturing processes are used for scaling down and high integration density, then device integration increases, but manufacturing complexity and difficulty of achieving uniformity increase
Solution Approach 1:
The substrate is divided into first and second regions with different critical dimensions, allowing each region to be optimized independently for its specific device requirements while maintaining overall manufacturing uniformity through the common sacrificial layer and spacer approach
Solution Approach 2:
A sacrificial layer is formed beforehand across the entire substrate before defining regions of different critical dimensions. This preliminary action enables subsequent selective removal and spacer formation that achieves uniform gate structures across regions with varying dimensions
Solution Approach 3:
Different critical dimensions are implemented in different regions (first region with first critical dimension, second region with second critical dimension) to optimize device performance for specific applications while maintaining manufacturing consistency through the overall process architecture
2Quantity of substance
If gate structures are formed across regions of varying critical dimensions, then high integration density is achieved, but uniformity of gate electrode height and surface integrity deteriorate
Solution Approach 1:
The sacrificial layer is formed uniformly across all regions before any region-specific patterning occurs. This preliminary uniform layer serves as a reference that ensures subsequent gate structures achieve consistent heights and surface integrity across regions with different critical dimensions
Solution Approach 2:
The sacrificial layer acts as an intermediary element that mediates between the substrate and the gate electrode formation process. By providing a uniform reference plane that is selectively removed, it enables precise control of gate electrode height and surface integrity across varying critical dimensions
Data Source
AI summary
A semiconductor device structure and a manufacturing method thereof are provided. The structure includes a substrate having a first region and a second region, first and second semiconductor channel sheets, first and second gate structure and source and drain regions. The first and second semiconductor channel sheets are disposed over the substrate and respectively in the first region and the second region. The first semiconductor channel sheets have a first channel width shorter than a second channel width of the second semiconductor channel sheets. The first and second gate structures are disposed over and laterally surrounding the first and second semiconductor channel sheets respectively. The first gate structure includes a first gate dielectric layer and a first metallic layer. The second gate structure includes a second gate dielectric layer and a second metallic layer. The source and drain regions are located beside the first and second semiconductor channel sheets. Tops of the first and second metallic layers are located at a same horizontal level.