HV LDNMOS Base Resistance Reduction via Localized P+ Source Doping
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Solution Overview
Problem
High voltage laterally double diffused metal oxide semiconductor (HV LDNMOS) devices have a limited safe operation area due to high base resistance and hot-hole current crowding, which restricts their performance in high voltage and high power applications.
Innovation Solution
The semiconductor device incorporates a doped source base region with a P-type or N-type conductivity, an N+ source region, and a P+ source region that is doped heavier and closer to the gate structure, reducing the base resistance of the parasitic bipolar junction transistor and alleviating hot-hole current crowding, thereby widening the safe operation area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional HV LDNMOS structure is used, then the device can be manufactured with standard processes, but the base resistance is high and hot-hole current crowding occurs, limiting the safe operation area
Solution Approach 1:
The patent introduces a P+ source region with higher doping concentration specifically at the source contact area, while maintaining the original P-type base region properties in other areas. This localized doping enhancement reduces base resistance where it matters most (at the source contact interface) without unnecessarily complicating the overall device structure or requiring additional processing steps beyond standard doping variations
Solution Approach 2:
The patent modifies the doping concentration parameter by introducing a P+ source region with higher acceptor concentration than the surrounding P-type base region. This parameter change directly reduces the base resistance and mitigates hot-hole current crowding effects, thereby expanding the safe operation area without fundamentally altering the device architecture
2Reliability
If the base resistance is reduced by increasing doping concentration, then the safe operation area increases, but the device structure becomes more complex
Solution Approach 1:
The P+ source region is formed during the standard manufacturing process sequence, integrating the base resistance reduction action into the existing fabrication flow. By incorporating this doping step into the preliminary manufacturing actions rather than adding a separate post-processing step, the patent achieves lower base resistance without significantly complicating the overall manufacturing process
Data Source
AI summary
A semiconductor device for a high voltage application includes a doped source base region, an N+ source region, a P+ source region and a gate structure. The doped source base region has P-type. The N+ source region extends downwards into the doped source base region. The P+ source region is close to the N+ source region, extends downwards into the doped source base region, and is doped heavier than the doped source base region. The gate structure is coupled to the N+ source region and is near to the P+ source region.