Split-Gate Flash Memory Array for Selective Byte Erase
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing non-volatile memory array architectures require erasing and reprogramming an entire row of memory cells to change information in a single byte, lacking the ability to selectively erase just a portion of a row.
Innovation Solution
The memory device architecture includes sub source lines and select transistors that allow for selective erasure of a single subrow of memory cells by isolating and controlling voltage application to specific regions within a row, enabling erasure of a single memory cell segment without affecting other cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If conventional memory array architecture is used, then entire row erasure is achieved, but data loss occurs in non-targeted cells
Solution Approach 1:
The source line is divided into multiple sub-source lines (first sub source line, second sub source line, etc.), each serving a specific column segment. This segmentation allows independent voltage application to different column regions, enabling selective erasure of only the desired memory cells while leaving other cells unaffected.
Solution Approach 2:
Select transistors are introduced as intermediary devices between the sub-source lines and the memory cells. These transistors act as controlled switches that regulate voltage distribution to specific column segments, providing precise control over which memory cells undergo erasure while protecting others from unwanted voltage exposure.
2Productivity
If conventional memory array architecture is used, then row-level erasure is implemented, but memory array efficiency decreases
Solution Approach 1:
The memory array architecture is segmented into multiple independent column segments through sub-source lines and select transistors. This enables parallel or selective operation on different segments, improving overall productivity by allowing targeted erasure operations without requiring complete row erasure, thus reducing unnecessary data loss and reprogramming overhead.
Solution Approach 2:
The architecture introduces dynamic control capability through select transistors that can be independently activated or deactivated. This dynamic control allows the system to adaptively select which column segments require erasure based on actual data modification needs, optimizing memory array efficiency by performing only necessary operations.
3Ease of operation
If sub source lines and select transistors are added, then selective erasure capability is improved, but device complexity increases
Solution Approach 1:
The source line is divided into multiple sub-source lines, each serving a specific column segment. This segmentation enables independent control of voltage application to different regions, providing selective erasure capability while maintaining a relatively simple overall architecture that builds upon the conventional memory cell structure.
Solution Approach 2:
The sub-source lines and select transistors serve multiple functions: they enable selective erasure operations, provide column-selective voltage distribution, and maintain compatibility with existing memory cell structures. This multi-functionality reduces the need for additional specialized components, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This architecture allows for precise erasure and programming of individual memory cells within a row, reducing unnecessary data loss and improving memory array efficiency by enabling selective data modification without disturbing other memory cells.
Implementation Method 1
The memory cell is erased (where electrons are removed from the floating gate 20) by placing a high positive voltage on the erase gate 30, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the edge of the floating gate 20 to the erase gate 22 via Fowler-Nordheim tunneling
Implementation Method 2
The electrons will accelerate and become heated when they reach the gap between the select gate 28 and the floating gate 20. Some of the heated electrons will be injected through the intermediate insulation onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A memory cell array with memory cells arranged in rows and columns, first sub source lines each connecting together the source regions in one of the rows and in a first plurality of the columns, second sub source lines each connecting together the source regions in one of the rows and in a second plurality of the columns, a first and second erase gate lines each connecting together all of the erase gates in the first and second plurality of the columns respectively, first select transistors each connected between one of first sub source lines and one of a plurality of source lines, second select transistors each connected between one of second sub source lines and one of the source lines, first select transistor line connected to gates of the first select transistors, and a second select transistor line connected to gates of the second select transistors.