Self-Aligned Inner Spacer for Defect-Reduced GAA Source/Drain Growth
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Solution Overview
Problem
The fabrication of gate-all-around (GAA) transistors faces challenges due to poor epitaxial source and drain (S/D) growth, which results in mobility reduction and performance degradation caused by rough surface defects in the S/D region interface.
Innovation Solution
The formation of self-aligned inner spacers by reflowing semiconductor layers provides a smooth S/D region interface, optimizing epitaxial growth and reducing defects, achieved through a method involving the reflow of semiconductor layers to form continuous sidewall surfaces for improved S/D feature growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for GAA transistors, then gate control is improved by increasing gate-channel coupling, but poor epitaxial source and drain growth occurs due to rough surface defects
Solution Approach 1:
The method performs preliminary surface preparation by forming a sacrificial layer and performing selective etching to create a smooth template surface before epitaxial growth. This preliminary action ensures that the surface is properly prepared in advance, preventing roughness defects during subsequent S/D growth while maintaining gate control benefits
2Productivity
If epitaxial source and drain growth is performed on rough surfaces, then device fabrication is completed, but mobility reduction occurs due to surface defects
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary element between the substrate and the epitaxial S/D growth. This sacrificial layer serves as a mediator that provides a smooth growth interface, enabling high-quality epitaxial growth while protecting the underlying structure. The intermediary layer is later removed to complete the device fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the smoothness of the S/D region surface, leading to uniform epitaxial growth of S/D features, reducing defects and improving the performance of GAA devices by mitigating mobility reduction and enhancing overall device performance.
Implementation Method 1
performing a reflow process to the first semiconductor layer to form an inner spacer
Implementation Method 2
epitaxially growing a source/drain feature in the source/drain region
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.