Stress Memorization Technique for pFET Channel Compressive Stress
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Solution Overview
Problem
The Stress Memorization Technique (SMT) is currently limited to nFETs as materials used for applying stress provide tensile stress at high temperatures, making it difficult to apply compressive stress to pFETs, which is necessary to enhance hole mobility and overall semiconductor performance.
Innovation Solution
A method involving the formation of a tensile-stressed layer on a p-type field effect transistor, selective etching to create compressive stress in the channel, and annealing to memorize the stress, using materials like Si3N4 and SiO2, combined with lithography and etching processes to achieve compressive stress in pFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional stress-inducing materials (such as nitride) are used for Stress Memorization Technique, then tensile stress can be applied to nFETs, but compressive stress cannot be applied to pFETs
Solution Approach 1:
The patent applies inversion by using a tensile-stressed layer (which normally provides tensile stress) to generate compressive stress in the channel through selective removal. By inverting the expected stress effect through strategic layer removal, the method enables compressive stress application to pFETs using materials traditionally used for tensile stress
Solution Approach 2:
The patent segments the stress-inducing layer into different regions - a first region over the channel and a second region over the source/drain regions. By selectively removing portions of these segments, different stress states are created in different areas, enabling compressive stress in the channel while maintaining structural integrity
2Reliability
If a tensile-stressed layer is formed and partially removed to generate compressive stress, then compressive stress can be applied to pFET channels, but the process complexity increases
Solution Approach 1:
The patent merges multiple functions into the tensile-stressed layer: it serves as both the stress-inducing layer and the etching stop layer. This consolidation reduces the total number of layers and process steps required, as the same layer provides both mechanical stress function and process control function
Solution Approach 2:
The tensile-stressed layer is designed to perform multiple functions simultaneously: providing tensile stress to the structure, serving as an etching stop layer to protect underlying layers, and enabling compressive stress generation through selective removal. This multi-functionality simplifies the overall device structure and manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases hole mobility and improves the overall performance of semiconductor structures by memorizing compressive stress in the channel of pFETs, making it suitable for industrial application.
Implementation Method 1
performing annealing so that the stress is memorized at the respective locations
Implementation Method 2
tensile stress may increase mobility of electrons, and thus driving current of an nFET, while compressive stress may increase mobility of holes
Implementation Method 3
performing annealing so that the stress is memorized at the respective locations, such as a gate region or an extension region
Implementation Method 4
the tensile-stressed layer is formed by a deposition process
Implementation Method 5
etching the tensile-stressed layer with the photoresist layer having the predetermined pattern as a mask
Data Source
AI summary
The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure.