Semiconductor Storage Power Supply Protection Circuit
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Solution Overview
Problem
Semiconductor storage devices face challenges in managing power supply voltages effectively, leading to unintended through-currents during power-on due to the use of RCTMOS circuits that forcibly short-circuit power supplies, which can result in transistor damage from ESD stress and inefficient voltage management across stacked chips.
Innovation Solution
The semiconductor storage device incorporates a power supply protection circuit with transistors and capacitors that manage voltage levels across pads P1 and P2, ensuring that transistors are in the correct state to prevent through-currents, with specific configurations for each chip to handle voltage surges and stabilize operations, including the use of transistors like Tr9 and Tr12 to control current flow based on voltage levels and the presence or absence of voltage VCCQ.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RCTMOS circuits are used to protect against ESD stress, then reliability is improved, but through-currents occur during power-on causing transistor damage
Solution Approach 1:
The patent applies preliminary action by detecting voltage surges before they cause harmful through-currents. The power supply protection circuit monitors voltage levels at pads and activates protection transistors in advance when abnormal voltage changes are detected, preventing the harmful effect rather than reacting after damage occurs.
Solution Approach 2:
The patent implements feedback mechanisms where the power supply protection circuit continuously monitors voltage levels at pads P1 and P2, and adjusts transistor states based on detected voltage conditions. This feedback loop ensures protection is activated only when necessary, preventing through-currents while avoiding unnecessary interference with normal operation.
2Reliability
If power supply protection circuits are provided for each chip, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges power supply protection functions across multiple chips by implementing a unified protection architecture. Instead of providing completely independent protection circuits for each chip, the invention combines protection resources at the channel level, allowing multiple chips to share common protection mechanisms while maintaining individual protection capabilities.
Solution Approach 2:
The patent applies universality by designing power supply protection circuits that can serve multiple functions and multiple chips simultaneously. The protection circuit is configured to monitor and protect various pads across different chips in a channel, making a single protection infrastructure serve multiple protection needs rather than requiring dedicated circuits for each chip.
3Reliability
If voltage management is implemented for each chip, then reliability is improved, but circuit area increases
Solution Approach 1:
The patent combines voltage management functions across multiple chips by implementing shared voltage monitoring and control circuits. Instead of duplicating complete voltage management infrastructure in each chip, the invention merges control logic and sensing mechanisms at the channel level, reducing redundant circuit area while maintaining comprehensive voltage management for all chips.
Solution Approach 2:
The patent transitions from chip-level distributed voltage management to channel-level centralized management, representing a dimensional change in the organization of voltage control. By moving the management function from two-dimensional chip surfaces to a higher-level channel architecture, the invention reduces total circuit area while maintaining or improving voltage management effectiveness.
Data Source
AI summary
According to an embodiment, a semiconductor storage device includes a first chip including a power supply protection circuit. The power supply protection circuit including: a resistor including a first end connected to the second pad; a first capacitor including a first end connected to a second end of the resistor; a first transistor including a first end connected to the second pad, a second end connected to a node with a signal of a value based on a voltage of the first end of the first capacitor, and a gate connected to the first pad; a first inverter including an input terminal connected to the second end of the first transistor; and a second transistor including a gate connected to an output terminal of the first inverter.