GAA Source-Drain Contact Layout for Tighter NFET-PFET Spacing
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Solution Overview
Problem
The challenge in scaling down Gate-All-Around (GAA) nanosheet technology is the minimization of NFET-to-PFET space in the Y-direction while preventing contact shorts between adjacent devices, due to the decreasing pitch leading to increased misalignment and defects.
Innovation Solution
The formation of a combined contact over the source/drain between devices, followed by cutting it to create separate contacts, allows for a dielectric layer to be formed between contacts and source/drains, reducing misalignment chances and preventing shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the pitch between adjacent devices is reduced to minimize NFET-to-PFET space, then device density is improved, but contact misalignment and shorts between adjacent devices increase
Solution Approach 1:
The patent performs preliminary actions by forming a combined contact structure that encompasses both adjacent device contacts before separation. The combined contact is formed with extended dimensions that cover both contact regions, ensuring proper alignment is established early in the process when misalignment risks are highest. Subsequent separation and dielectric formation steps then work within this pre-established alignment framework.
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the separated contacts and source/drain regions. This dielectric layer acts as a buffer that compensates for any residual misalignment, preventing direct contact between adjacent device contacts and eliminating short circuits. The intermediary layer provides a tolerance buffer that allows tighter pitch while maintaining manufacturing precision.
2Ease of manufacture
If separate contacts are formed directly over source/drain regions, then contact alignment is simplified, but misalignment between adjacent contacts increases leading to shorts
Solution Approach 1:
The patent merges the formation of adjacent device contacts into a single combined contact structure. Instead of forming separate contacts independently, the combined contact is formed as one continuous structure that spans multiple contact regions. This merging approach simplifies the formation process while the subsequent separation and dielectric insertion maintain reliability by preventing shorts between adjacent devices.
Solution Approach 2:
The patent segments the combined contact into separate individual contacts after the combined structure has been formed and aligned. This segmentation occurs after the alignment-critical formation step, allowing the contacts to be divided into separate entities with dielectric material inserted between them. The segmentation maintains the alignment benefits of the combined formation while achieving the isolation benefits of separate contacts.
3Productivity
If tighter pitch is used to increase device density, then space utilization is improved, but the likelihood of contact shorts between adjacent devices increases
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary barrier between adjacent contacts and source/drain regions. This dielectric intermediary prevents direct electrical contact between adjacent devices, eliminating the harmful short circuit effect. The intermediary layer provides physical and electrical isolation that enables tighter pitch by compensating for reduced spacing between devices.
Solution Approach 2:
The patent applies beforehand cushioning by forming the dielectric layer between contacts and source/drain regions before final device operation. This preventive measure cushions against potential misalignment and ensures isolation is established prior to any operational stresses. The dielectric cushioning layer provides a safety margin that prevents shorts even when pitch is reduced for higher device density.
Data Source
AI summary
A semiconductor device including a first nanodevice is located on a substrate, where the first nanodevice includes at least one channel. A first source/drain connected to the first nanodevice. A second nanodevice located on the substrate, where the second nanodevice includes at least one channel and a second source/drain connected to the second nanodevice. A first contact located above the first source/drain. A second contact located above the second source/drain. A contact cap located on top of the first contact and the second contact, where the contact cap has a first leg that extends downwards between the first contact and the second contact. The first leg of the contact cap is in contact with a first sidewall of the first contact, and a first sidewall of the second contact.