Vertical Memory Transistor Layout for Higher Cell Density
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Solution Overview
Problem
Conventional 1T-1X memory cells face limitations in density due to the constraints of forming FEOL transistors on a semiconductor substrate, leading to increasing process complexity and cost, which hinders the scaling of memory density.
Innovation Solution
The implementation of memory devices with vertical transistors, where the bitline acts as a source/drain region and the wordline as a gate electrode, utilizing aspect ratio trapping to prevent defect expansion into the channel region, allowing for a more compact and dense memory cell arrangement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional front-end-of-line transistors are used to form memory cells, then the memory device can be manufactured with existing processes, but the memory cell density is limited due to the finite number of transistors that can be formed on a substrate
Solution Approach 1:
The patent transitions from planar transistors to vertical transistors, utilizing the third dimension (vertical direction) to increase the number of transistors that can be formed on a substrate. The vertical transistor structure extends in the vertical direction with a channel region, source region, and drain region stacked vertically, allowing higher density memory cell formation without increasing lateral footprint
Solution Approach 2:
The bitline serves multiple functions: it acts as both a source/drain region and a conductive interconnect. The wordline functions as both a gate electrode and a select line for memory cell access. This multi-functionality reduces the number of separate components needed, simplifying the overall device structure while increasing density
2Quantity of substance
If more transistors are formed on the substrate to increase memory density, then memory cell density improves, but process complexity increases and scaling returns diminish
Solution Approach 1:
By forming transistors vertically rather than laterally, the patent enables more transistors to be packed onto a substrate without requiring increasingly complex lateral scaling processes. The vertical orientation allows standard planar fabrication processes to be adapted for three-dimensional structures, maintaining manufacturing feasibility while achieving higher transistor counts
Solution Approach 2:
The vertical transistor is segmented into distinct functional regions (source region, channel region, drain region) that can be formed through sequential processing steps. This segmentation allows each region to be optimized independently while using standard semiconductor fabrication techniques, making the manufacturing process manageable despite the increased complexity
3Area of moving object
If vertical transistors with aspect ratio trapping design are used, then memory cell area is reduced to 4F2 or 6F2, but the transistor structure becomes more complex
Solution Approach 1:
The patent merges the bitline with the source/drain region and the wordline with the gate electrode, reducing the number of separate components. The aspect ratio trapping design combines the source/drain regions in a compact vertical arrangement that shares common structures, thereby minimizing the lateral footprint to 4F2 or 6F2 while managing structural complexity through integration
Solution Approach 2:
The vertical transistor structure employs a nested arrangement where the channel region is surrounded by the source/drain regions in a compact configuration. The gate electrode wraps around or is positioned to control the channel region, creating a nested geometry that maximizes control while minimizing the lateral area occupied by each transistor
4Quantity of substance
If vertical transistors are implemented to increase density, then more transistors fit in the same area, but standby power consumption must be managed
Solution Approach 1:
The vertical transistor structure enables more efficient gate control with the wordline, allowing for better timing and control of transistor switching. The compact vertical geometry improves gate-to-channel coupling, enabling more precise control over when current flows, thereby reducing leakage and standby power consumption while maintaining high density
Solution Approach 2:
The vertical transistor design changes the geometric parameters (aspect ratio, vertical dimensions) to improve electrical characteristics. The high aspect ratio vertical structure enhances gate control efficiency and reduces off-state leakage current, thereby lowering standby power consumption while achieving higher transistor density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory cell density, enabling higher packing density and efficient operation in both low-power and high-power applications while maintaining conductivity and reducing defect impact.
Implementation Method 1
an insulator wrapped around at least a portion of the channel region
Implementation Method 2
utilizing aspect ratio trapping to prevent defect expansion into the channel region
Data Source
AI summary
Memory devices including vertical transistors and methods of forming such memory devices are disclosed. An example memory device includes a substrate, a BL in the substrate, a channel region over a portion of the BL, a second region over the channel region, an insulator wrapped around at least a portion of the channel region, and a WL. The BL also operates as one of a source region and a drain region of the transistor. The second region is the other one of the source region and the drain region. The WL wraps around at least a portion of the insulator and is separated from the channel region by the insulator. In some embodiments, the BL is formed in a trench in the substrate. An aspect ratio of the BL is in a range from 0.5 to 10. The BL may have a higher conductivity than the channel region.