Metal Gate N/P Boundary Control Using Active Gate Cut Recess
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Solution Overview
Problem
Advanced nonplanar transistor architectures, such as FinFETs and nanosheet FETs, face challenges in controlling tightly spaced N/P boundaries and work function metal patterning, leading to difficulties in scaling semiconductor devices due to issues like undesirable removal of work function metal from masked or blocked regions.
Innovation Solution
The implementation of an active gate cut and recess processing scheme, where a dielectric gate cut is inserted at the N/P boundary before work function metal patterning, allowing for precise control and replacement with conductive material to ensure electrical continuity across the boundary without over-etching, and the recess height can be tuned to maintain threshold voltage and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional work function metal patterning is used in tightly spaced N/P boundaries, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to undesirable removal of work function metal from masked or blocked regions
Solution Approach 1:
The gate structure is segmented by introducing a gate cut that divides the gate into separate regions over the N-type and P-type FETs. This segmentation allows independent work function metal patterning in each region, preventing unwanted metal removal at the N/P boundary while maintaining manufacturing precision.
Solution Approach 2:
The gate cut and recess structure is formed preliminarily before work function metal deposition. This preliminary action creates a physical barrier that prevents work function metal from being deposited or removed in unwanted areas, ensuring precise patterning without requiring complex masking steps during metal processing.
2Productivity
If device scaling is pursued to increase density, then productivity is improved, but manufacturing precision deteriorates due to difficulties in controlling tightly spaced N/P boundaries
Solution Approach 1:
By segmenting the gate structure with a gate cut at the N/P boundary, the patent enables independent processing of N-type and P-type regions. This segmentation maintains manufacturing precision even as devices are scaled closer together, allowing high device density without sacrificing boundary control.
Solution Approach 2:
The gate cut and recess structure provides local quality differentiation at the N/P boundary region. The recessed gate cut allows for localized work function metal deposition and patterning, ensuring precise N/P boundary control while enabling tighter device spacing for increased productivity.
3Manufacturing precision
If work function metal is removed from tight spaces to improve boundary control, then manufacturing precision is improved, but electrical continuity deteriorates due to potential disruption at the N/P boundary
Solution Approach 1:
The gate cut recess structure acts as an intermediary element at the N/P boundary. It provides a controlled interface that allows work function metal patterning precision while maintaining electrical continuity through the gate structure, preventing disruption at the boundary between N-type and P-type regions.
Data Source
AI summary
Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.