3D Memory Cell Structure for Threshold Voltage Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face issues with trap centers forming at the interface of semiconductor-insulator contacts, leading to shifted threshold voltages and reduced reliability, while also requiring larger area and higher manufacturing costs.
Innovation Solution
A semiconductor device design featuring concentrically arranged insulators and semiconductors on the side surfaces of conductors, with specific conductor configurations to form transistors, enhancing reliability and reducing area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a plurality of memory elements are stacked and connected in series to form a three-dimensional memory cell array, then storage capacity per unit area is increased, but trap centers form at the interface between semiconductor and insulator, leading to shifted threshold voltage and reduced reliability
Solution Approach 1:
A fourth conductor is introduced as an intermediary layer between the first conductor and the first semiconductor in the second region. This intermediate conductor structure modifies the electric field distribution and reduces direct contact between the first conductor and first semiconductor, thereby minimizing trap center formation at the interface while preserving the stacked memory cell configuration for high storage capacity
Solution Approach 2:
The fourth conductor is selectively provided only in the second region where the first conductor overlaps with the third conductor, rather than throughout the entire structure. This localized modification targets specific areas where trap centers are most problematic, optimizing threshold voltage stability without compromising the overall stacked memory architecture
2Area of stationary object
If memory cells are stacked vertically to increase storage capacity, then the area occupied by the memory device is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The stacked memory structure is divided into distinct regions (first region and second region) with different conductor configurations. The fourth conductor is selectively implemented only in the second region, allowing the device to achieve high vertical integration for small footprint while simplifying manufacturing by avoiding unnecessary complex structures in the first region
Data Source
AI summary
A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.