Read-Only Memories TRIZ Cases

Multiple current mirrors generate separate programming and read bias levels, preventing OTP read failures after anti-fuse resistance rises.

Multi-loop duty correction in a memory buffer chip aligns data strobe timing across non-volatile memories, improving synchronized transfer efficiency.

Remanent polarization in FeFET memory states shifts threshold voltage to tune signal delay without extra transistors, capacitors, or routing.

Distinct threshold-voltage switch elements generate current levels for accurate, efficient AI data search with manageable memory-string complexity.

Gray code counting, wear levelling, and majority voting cut counter memory demand while preserving reliable operation in error-prone non-volatile memory.

Gray code counting, wear levelling, and majority voting cut counter memory demand while preserving error tolerance in non-volatile memory.

A configurable RC wordline underdrive slows voltage transitions to cut SRAM power use while improving read and write access stability.

Shifting TDC input timing and correcting delay-stage errors reduces PVT and voltage-drop effects in distance measurement.

A gate discharge circuit keeps bit line and source line voltage difference controlled after erase, preventing junction breakdown and FN stress.

Integrating clock and data pads with an in-cell flip-flop cuts serial path delay and improves synchronization for faster data output.

Phase comparison adjusts clock delay intervals to cut jitter and preserve signal integrity in high-speed memory modules.

A two-stage amplifier with pull-up and pull-down feedback cuts circuit area and elements while supporting fast, low-power 3D memory operation.

A pre-charging current proportional to the reference current cuts data-line settling time while avoiding over-precharge errors in memory sensing.

Selective bit-line switching isolates the target flash FPGA cell during programming, preventing threshold drift and added signal delay.

A switchable pull-down on the link startup mode pad prevents leakage and keeps storage interface voltage levels stable across low- and high-speed modes.

A controllable pull-down resistor stabilizes a storage interface startup pad, preventing current leakage and link mode faults.

A fitted tempco equation replaces large lookup tables and adapts each memory die across erase cycles to reduce raw bit errors.

Retained page-buffer node voltages adjust data-line levels to narrow flash threshold distributions without SSPC subset complexity or extra verify time.

A capacitive pull-down circuit drives an SRAM ground node below 0 V during read and write operations to improve voltage margin and stability.

A gate-controlled MOSFET discharge path stabilizes post-erase bit and source line discharge to avoid junction breakdown and Fowler-Nordheim stress.

Asynchronous multi-plane read units and a multiplexing circuit let NAND Flash accept reads while busy, improving flexibility and throughput.

Splitting input signals into MSB and LSB analog voltages lets aCAM circuits expand programmable levels without added hardware complexity.

Measured current demand guides deboost and precharge adjustment, improving multi-level NAND cell state sensing under threshold shifts.

Pre-emphasis adds undershoot and overshoot to steepen differential signal transitions, raising speed while limiting power and heat.

Stacked pass gates and NMOS selectors split programming voltage across core devices, protecting memory arrays from breakdown stress while saving area.

Negative-feedback transistors compensate n-type mismatch in a DRAM sense amplifier, improving linearity, speed, and read accuracy.

A ring counter deserializer cuts flip-flop count to shrink memory I/O area, lower power, and reduce peak current.

Routes DAC-generated analog signals to selected memory-array rows, cutting bulky CMOS circuitry while improving neural network energy efficiency and scalability.

Clock phase adjustment lets flip-flops capture symbol heads without large multiplexers or buffering, reducing serial-to-parallel alignment delay.

Time-delay circuits stagger high-voltage switching and bit-line sensing to limit peak current and prevent non-volatile memory errors.

A differential sense amplifier and controlled reference bit line speed ROM reads while keeping bit cells small, leakage low, and area compact.

Maintains a constant gate-to-source voltage during NAND erase discharge to prevent junction breakdown and Fowler-Nordheim stress.

A parallel source follower balances differential amplifier rise and fall response to cut jitter and duty cycle distortion in memory interfaces.

Electric-field-programmable threshold transistors replace SRAM in FPGA LUT cells to cut leakage, shrink cell area, and retain data without power.

A temporary reference voltage stabilizes oscillator supply during startup, cutting NAND read transfer delay and clock frequency variation.

Controlled bit-line discharge uses a current mirror and staggered enable signals to prevent peak current and shorten Flash memory discharge time.

Intermediate cancellation voltage levels shrink PAM transition steps, improving data eye margins, decoding reliability, and signaling speed.

Separate detection paths let memory output handle normal and state reads while preserving layout margin and lowering current consumption.

Training multi-phase clocks with monitoring signals corrects duty and skew distortion, widening valid timing margins for stable high-speed memory operation.

By training duty and skew in multi-phase clocks before operation, the controller preserves valid window margin for stable high-speed memory transfer.

Series MOSFETs and level shifters let non-volatile memory program from internal or external power while blocking leakage currents.

Adaptive pin termination and multi-amplitude signal detection improve NAND memory transfer quality while avoiding unnecessary termination overhead.

Parallel transistors with different threshold voltages block I/O driver leakage current while preserving memory performance and data integrity.

A shared non-regular counter and selectable reference voltages stabilize memory sensing timing across bit-line current variation and reduce storage errors.

Memristor-based differentiable analog CAM cuts power use while a learning algorithm improves search precision without losing CAM speed.

Multiple voltage generators validate when a reference voltage is stable, reducing PVT-driven false POR triggers in memory subsystems.

Word-addressable NVM lets programmable logic retain configuration and user data after power loss while supporting random memory access.

Modified doping creates higher floating-gate channel resistance than the select transistor, improving programming and erasing efficiency.

Dynamic pin termination switches on for low-amplitude signals and off for larger signals to improve NAND memory signal integrity without constant power draw.

A unified input buffer handles differential and single-ended memory signals on one path, cutting interference, layout complexity, and power use.