Memory I/O Power Gating Circuit for Leakage Current Blocking
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Solution Overview
Problem
Nonvolatile semiconductor memory devices experience leakage currents in their input/output circuits during data transfer, which can lead to data loss and inefficiencies.
Innovation Solution
Incorporation of a power gating circuit with multiple transistors having different threshold voltages, connected in parallel, to block leakage currents in the driver transistors of the input/output circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a single high-threshold transistor is used to block leakage current, then leakage current is reduced, but the transistor area increases significantly
Solution Approach 1:
The power gating transistor is divided into multiple transistors connected in parallel, each with progressively lower threshold voltages. This segmentation allows the system to achieve effective leakage blocking without requiring a single large-area high-threshold transistor, as each smaller transistor contributes to the overall leakage reduction while maintaining compact dimensions.
Solution Approach 2:
Different transistors within the parallel configuration have different threshold voltage characteristics tailored to specific leakage conditions. This local quality differentiation allows each transistor to optimize its contribution to leakage blocking, with lower-threshold transistors handling specific leakage paths while maintaining overall area efficiency.
2Object-generated harmful factors
If multiple transistors with different threshold voltages are used in parallel, then leakage current blocking is improved, but device complexity increases
Solution Approach 1:
The power gating function is segmented into multiple parallel transistor paths with different threshold voltages. This segmentation approach simplifies the overall control logic compared to using a single complex high-threshold transistor, as each parallel path can be independently controlled and optimized for specific leakage conditions.
Data Source
AI summary
An input/output circuit of a nonvolatile memory device and a nonvolatile memory device. The input/output circuit of a nonvolatile memory device includes a driver, which is configured to output data from the nonvolatile memory device to a data line, and a power gating circuit, which is connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver. The power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively.