Differential ROM Sensing for Fast Reads in Small Bit Cells
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Solution Overview
Problem
Existing ROM technologies face a tradeoff between read access time and circuit area, with smaller bit cells offering better density but slower performance due to increased local mismatch, while larger bit cells provide faster performance at the expense of increased circuit area and leakage.
Innovation Solution
A semiconductor device incorporating a ROM with a differential sense amplifier and multiplexer logic circuit, where memory cells are arranged in an array with reference cells, allowing for differential output voltage generation and selective coupling of bit lines to control reference currents, thereby improving read access times without significant increases in circuit area or leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If smaller ROM bit cells are used to improve density, then circuit area is reduced, but read access time increases due to increased local mismatch
Solution Approach 1:
The invention segments the bit line current into two separate current mirrors: one for the selected bit line and one for the reference bit line. This segmentation allows independent optimization of each current path, enabling the use of smaller bit cells without compromising read access time. The differential sense amplifier compares these segmented currents to detect stored data, resolving the contradiction between small cell size and fast read access.
Solution Approach 2:
The invention introduces reference cells and a reference bit line as intermediary elements between the memory cells and the sense amplifier. These intermediaries provide a stable reference current that compensates for the increased local mismatch in smaller bit cells. The multiplexer logic circuit selectively couples the reference bit line to the sense amplifier, enabling accurate data detection despite the reduced bit cell size.
2Speed
If larger ROM bit cells are used to improve read access time, then read speed increases, but circuit area and leakage increase
Solution Approach 1:
The invention segments the current sensing function into separate current mirrors for signal and reference bit lines. This allows the use of smaller bit cells with faster read access time, while the segmented current mirror structure compensates for the reduced cell size effects, eliminating the need for larger bit cells and their associated area penalties.
Solution Approach 2:
The invention changes the sensing parameter from voltage-based to current-based differential sensing. By using current mirrors to sense and compare bit line currents rather than voltages, the system achieves faster read access time with smaller bit cells, as current sensing is less susceptible to the local mismatch effects that plague voltage sensing in small cells.
3Speed
If larger ROM bit cells are used to improve read access time, then read speed increases, but leakage increases
Solution Approach 1:
The invention segments the bit line current sensing into separate current mirrors, allowing smaller bit cells to be used. This segmentation enables faster read access time without requiring larger cells that would increase leakage. The separate reference current mirror compensates for mismatch effects in small cells, achieving fast read access with minimal leakage.
4Speed
If differential sense amplifier with reference current is used to improve read access time, then read speed increases, but device complexity increases
Solution Approach 1:
The invention uses a universal current mirror structure that serves multiple functions: sensing bit line current, generating reference current, and providing differential comparison. This multi-functional current mirror design achieves fast read access time without proportionally increasing device complexity, as the same basic current mirror topology is reused throughout the circuit.
Solution Approach 2:
The invention creates equipotential conditions by using matched current mirrors for both the selected bit line and reference bit line. This equipotential approach simplifies the differential sensing operation, as the current mirrors naturally balance the circuit under normal conditions, requiring only simple control logic to detect data states and reducing overall device complexity.
Data Source
AI summary
A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.